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INTEGRATED CURCUITS
DATA SHEET
SC4000 Universal Timeslot Interchange
Preliminary specification File under Integrated Curcuits 2000 Sep 07
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Logic Pin Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 SC4000 100-Pin TQFP (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......................... . . . . . . . . . . . . . . . . . . . . . . . . . . 2 SC4000 Physical Dimensions (all dimensions in millimeters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...................... . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 PLL Timing and Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Interrupts Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 CLKFAIL Timing and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Message Channel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Operation Mode and Configuration Register Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Register Access Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . 17
I/O Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Busy (D_0) (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Read (D_1) (Write only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write (D_2) (Write only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Terminate (D_3) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......................... . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Channel Bank Select Register [1:0] (D_[5:4]) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . 17 Channel Bank Select Register Enable (D_6) (Write only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Reset (D_7) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Channel Specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Time-Slot Select [6:0] (Read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Port Select [3:0] (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Parallel Access Enable (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Switch Output Enable (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Time-Slot/Channel Select [6:0] (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . 20 Port Select [3:0] (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Local Connect Enable (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Switch Output Enable (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Parallel Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Serial Data [1:8] (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Source Parallel Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Serial Data [1:8] (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2000 Sep 07
2
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SCbus Clock Master (C_0) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SCbus Clock Master Arm (C_1) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SCbus Primary/Alternate Select (C_2) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . 21 Diagnostic Mode Enable (C_3) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SCbus Framing Mode [1:0](C_[5:4]) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . 21 Local bus Framing Mode [1:0](C_[7:6]) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . 21 Master Clock Input Frequency Select [2:0] (C_[10:8]) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Direct R/W to Parallel Access Registers Enable (C_11) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Message Channel Registered TXD Enable (C_12) (Read/Write) . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . 21 Message Channel TXD_0 or TXD_1 Select (C_13) (Read/Write) . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . 22 Message Channel Clock Duty Cycle Select (C_14) (Read/Write) . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . 22 Message Channel Output Disable (W/ loopback) (C_15) (Read/Write) . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . 22 SCbus SD Sample Position (C_16) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Local Bus SI Sample Position (C_17) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SCbus SD Output Delay Enable (C_18) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . 22 Local bus SO Output Delay Enable (C_19) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . 22 SCbus FSYNCN Sample Position (C_20) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . 22 SCbus FSYNCN Rate (C_21) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . 22 SCbus SCLKX2N, SCLKX2NA Output Disable(C_22) (Read/Write) . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . 22 SCbus Alternate ("A") Signals Output Enable (C_23) (Read/Write) . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . 23 Local bus L_CLK Polarity (C_24) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . 23 Local bus L_FS Polarity (C_25) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . 23 Local bus L_FS Position (C_[27:26]) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . 23 Local bus L_CLK & L_FS Rate (C_28) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Local bus L_CLK DPLL Enable (C_29) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . 23 Local bus L_CLK 8.192 MHz 62.5% Duty Cycle (C_30) (Read/Write) . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . 23 Version/Revision Status (C_[39:32]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . 23 Master PLL Reference Select [2:0] (C_[42:40]) (Read/Write) . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . 23 Internal/External Master PLL Select (C_43) (Read/Write) . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . 24 SCbus SREF_8K Source Select [1:0] (C_[45:44]) (Read/Write) . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . 24 SCbus SREF_8K Output Enable (C_46) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . 24 SCbus SCLK 8.192 MHz 62.5% Duty Cycle (C_47) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Clock Watchdog Enable (C_48) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . 24 Microprocessor Watchdog Enable (C_49) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SCbus CLKFAIL Latch Set Polarity Select (C_50) (Read/Write) . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . 24 SCbus CLKFAIL Latch Debounce Enable (C_51) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Frame Boundary Latch Set Delay Enable (C_52) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 INT_0 Mask_N (C_53) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . 25 INT_0 Output Polarity (C_54) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . 25 INT_0 Output Driver (C_55) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SCbus CLKFAIL Latch (C_56) (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . 25 Frame Boundary Latch (C_57) (Read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . 25
2000 Sep 07
3
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Internal Master PLL Error Latch (C_58) (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SCbus Error Indicator (C_59) (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . 25 SCbus CLKFAIL Latch Clear_N (C_60) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . 25 Frame Boundary Latch Clear_N (C_61) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Internal Master PLL Error Latch Clear_N (C_62) (Read/Write) . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . 25 SCbus SCLKX2N Error Latch (C_64) (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SCbus SCLKX2NA Error Latch (C_65) (Read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SCbus SCLK Error Latch (C_66) (Read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . 26 SCbus SCLKA Error Latch (C_67) (Read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . 26 SCbus SCLKX2N Error Latch Clear_N (C_68) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SCbus SCLKX2NA Error Latch Clear_N (C_69) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SCbus SCLK Error Latch Clear_N (C_70) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SCbus SCLKA Error Latch Clear_N(C_71) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SCbus FSYNCN Error Latch (C_72) (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SCbus FSYNCNA Error Latch (C_73) (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SCbus Clock Master Error Latch (C_74) (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . 26 SCbus FSYNCN Error Latch Clear_N (C_76) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SCbus FSYNCNA Error Latch Clear_N (C_77) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SCbus Clock Master Error Latch Clear_N (C_78) (Read/Write) . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . 26 SCbus SREF_8K NE SREF_8KA Error Latch (C_80) (Read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SCbus CLKFAIL NE CLKFAILA Error Latch (C_81) (Read only) . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . 27 SCbus MC NE MCA Error Latch (C_82) (Read only) . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . 27 SCbus SD Error Indicator (C_83) (Read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............................ . . . . . . . . . . . . . . . . . . . . . 27 SCbus SREF_8K NE SREF_8KA Error Latch Clear_N (C_84) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SCbus CLKFAIL NE CLKFAILA Error Latch Clear_N (C_85) (Read/write) . . . . . . . . . . . . . . . .............................. . . . . . . . . . . . 27 SCbus MC NE MCA Error Latch Clear_N (C_86) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . 27 SCbus SD Error Latch Clear_N (C_87) (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . 27 SCbus SD_[15:0] Error Latch (C_[103:88]) (Read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Summary of SC4000 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 ..
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Master Clock/PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SCbus (MVIP Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Message Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Reserved Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............................ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Typical Internal Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................... . . . . . . . . . 28
Typical Write Internal Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . 28 Typical Read Internal Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
AC Electrical Characteristics
2000 Sep 07
4
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9.
SC4000
Configuration Register Setup for SCbus Clock Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. . . . . . . . . . . . . . 11 Configuration Register Setup for SCbus Clock Master. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. . . . . . . . . . . . . 12 Configuration Register Setup for SCbus Armed Clock Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. . . . . . . . . . 13 Configuration Register Setup for MVIP Clock Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. . . . . . . . . . . . . . 14 Configuration Register Setup for MVIP Clock Slave. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. . . . . . . . . . . . . . 14 SCbus/MVIP Signals Cross Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. . . . . . . . . . . . . . . . 15 Microprocessor Interface Timing - Intel Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Microprocessor Interface Timing - Intel Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Microprocessor Interface Timing - Multiplexed Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 10. Local Bus Timing, 1X L_CLK Mode (C_28=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 11. Local Bus Timing, 2X L_CLK Mode (C_28=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 12. SCbus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 13. SCbus Clock Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 14. SCbus Clock Fail Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. . . . . . . . . . . . . . . . . . . . . . . 39 Table 15. REF_8K_[3:0] and SREF_8K Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. . . . . . . . . . . . . . . . . . 40
2000 Sep 07
5
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9.
SC4000
Destination and Source Switch Function Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . 7 Internal Master PLL (C_43 = 0) Function Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . 8 External Master PLL (C_43 = 1) Function Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . 9 Internal PLL and Local Bus PLL Timing Function Block . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . 10 Using Two Pins A_[1:0] for Address Bus Interface Scheme (C_11 = 0) . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . 16 Using Nine Pins A_[8:0] for Address Bus Interface Scheme (C_11 = 1) . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . 16 Microprocessor Interface Timing - Intel Bus Mode (Pin I_N = 0), Non-Multiplexed Address . . . . . . . . . . . . . . . . . . . . . . 31 Microprocessor Interface Timing - Motorola Bus Mode (Pin I_N = 1), Non-multiplexed Address . . . . . . . . . . . . . . . . . . . 32 Microprocessor Interface Timing - Multiplexed Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 10. Local Bus Timing, 1XL_CLK Mode (C_28=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 11. Local Bus Timing, 2X L_CLK Mode (C_28=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 12. SCbus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 13. SCbus Clock Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . 38 Figure 14. SCbus Clock Fail Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 15. REF_8K_[3:0] and SREF_8K input mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . 40
2000 Sep 07
6
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
FEATURES * Timeslot interchange between local and expansion buses * Architecture optimized for call processing environments: SCbusTM, MVIP(R) and ST-BUS Compatible * Full switching between any of: - 128 local bus input SI timeslots - 128 local bus output SO timeslots - up to 2048 expansion bus SD timeslots * Multiple local bus speeds and formats: - 2.048, 4.096 or 8.192 Mb/s - PEB(R), STbus or GCI * Supports both Intel(R) and Motorola(R) processor interfaces * Serial or parallel access to expansion bus * Enhanced input hysteresis threshold * Internal phased lock loop * Fast response and support for SCbus clock fallback * Flexible local frame sync interface * Supports hyper channel capability (bundling) * SCbus message bus interface and local loopback control * High availability and self-diagnostic features * 5V CMOS technology * 100-pin TQFP package APPLICATIONS * PC-based switching
SC4000
* Small to medium size digital switch matrices * SCbus/MVIP interface functions * Digital centralized voice processing system * Voice/Data multiplexer and exchange * Computer telephony interface
Logic Pin Organization
44 43 42 40 39 38 36 35 34 32 31 30 28 27 26 25 24 22 17 16 19 20 21 96 12 2 1 7 6 5 4 95 94 92 91 9 98 D_7 D_6 D_5 D_4 D_3 D_2 D_1 D_0 A_8 A_7 A_6 A_5 A_4 A_3 A_2 A_1 A_0 ALE CS_1_N CS_0_N RD_N(STRB_N) WR_N(R/W_N) DACK_N RESET I_N(M) X_IN X_OUT REF_8K_3(REF_8K_OUT) REF_8K_2(CLK_IN) REF_8K_1 REF_8K_0 SI_3 SI_2 SI_1 SI_0 TXD_0 TEST INT_1 INT_0 (TEST_OUT_0)DRQ_R (TEST_OUT_1)DRQ_T SCLKX2N SCLKX2NA SCLK SCLKA SREF_8K SREF_8KA FSYNCN FSYNCNA CLKFAIL CLKFAILA SD_0 SD_1 SD_2 SD_3 SD_4 SD_5 SD_6 SD_7 SD_8 SD_9 SD_10 SD_11 SD_12 SD_13 SD_14 SD_15 MC MCA L_CLK L_FS SO_3 SO_2 SO_1 SO_0 MC_CLK RXD 15 14 99 100 46 47 49 50 51 52 54 55 56 58 59 60 62 63 64 66 67 68 70 71 72 74 75 76 77 79 80 81 83 84 90 88 87 86 11 10
SC4000
2000 Sep 07
7
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
Block Diagram SI_[3:0] 128 x 2048 Destination SD_[15:0]
SC4000
Switch
SO_[3:0] 128 x 2176 Source Switch Local Bus Timing Timing SCbus Timing Local Connect
CLK_IN REF_8K_[3:0]
DPLL
A_[8:0] D_[7:0] Control Micro Processor Interface
Control Bus
SC4000 100-Pin TQFP (top view)
SD_12 SD_11 VSS SD_10 SD_9 SD_8 VSS SD_7 SD_6 SD_5 VDD SD_4 SD_3 SD_2 VDD SD_1 SD_0 CLKFAILA VSS CLKFAIL FSYNCNA FSYNCN VSS SREF_8KA SERF_8K 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SD_13 SD_14 VDD SD_15 MC MCA VSS L_CLK L_FS VDD SO_0 SO_1 SO_2 VDD SO_3 SI_0 SI_1 VSS SI_2 SI_3 RESET VSS TEST DRQ_R DRQ_T
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
SC4000 100-PIN TQFP
(TOP VIEW)
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
SCLKA SCLK VDD SCLKX2NA SCLKX2N VSS D_7 D_6 D_5 VSS D_4 D_3 D_2 VDD D_1 D_0 A_8 VSS A_7 A_6 A_5 VDD A_4 A_3 A_2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1819 20 2122 23 24 25
2000 Sep 07
X_OUT X_IN VSS REF_8K_0 REF_8K_1 REF_8K_2 REF_8K_3 VDD TXD_0 RXD MC_CLK I_N VDD INT_0 INT_1 CS_0_N SC_1_N VSS RD_N WR_N DACK_N ALE VSS A_0 A_1
8
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000 Physical Dimensions (all dimensions in millimeters)
_ 16.00 + 0.40 _ 14.00 + 0.20
SC4000
1.00 REF _ 0.22 + 0.05 o 12 REF _ 1.40+ 0.05 0.25 _ 0.14 + 0.04 _ 16.00 + 0.40 _ 14.00 + 0.20
0.15 MAX 0.50 Typ o 12 REF
00- 10 0 _ 0.60 + 0.15 0.20 MIN
2000 Sep 07
9
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
PIN DESCRIPTION
Pin Name D_[7:0] A_[8:0] ALE CS_1_N CS_0_N I_N or M RD_N or STRB_N WR_N or R/W_N DACK_N RESET X_IN X_OUT REF_8K_3 or REF_8K_OUT REF_8K_2 or CLK_IN REF_8K_1 REF_8K_0 SI_[3:0] TXD_0 TEST INT_1 INT_0 Input/Output I/O I I I I I Pin Number 44,43,42,40, 39,38,36,35 34,32,31,30, 28,27,26,25,24 22 17 16 12 Pin Description
SC4000
(TTL Bi-directional) Microprocessor Data Bus. These bi-directional, tri-state lines allow the microprocessor to access SC4000 internal registers as well as the source/destination routing memory and parallel access registers. (TTL Input) Microprocessor Address Bus. These inputs select the internal registers used by a read or write operation. Normally these inputs are connected to Microprocessor address lines A[8:0]. (TTL Input) Address Latch Enable. This input pin is tied to high in non-multiplexed mode. Otherwise, in multiplexed mode, the Microprocessor Address Bus is latched internally on the falling edge of this signal. (TTL Input) Chip Select 1. Reserved for future internal HDLC controller. If unused, this pin should be connected to high. (TTL Input) Chip Select 0. This active low signal selects the SC4000 for a microprocessor read or write operation. (TTL Input) Microprocessor Bus Interface Mode Select. When this input is low, Intel Bus Mode (I_N) is selected. When this input is high, Motorola Bus (M) Mode is selected. (TTL Input) In Intel Bus Mode (RD_N), this active low input operates with CS_0_N to configure the data bus lines D_[7:0] as output. In Motorola Bus Mode (STRB_N), this active low input operates with CS_0_N to enable a read or write operation. (TTL Input) In Intel Bus Mode (WR_N), when CS_0_N is active, the rising edge of WR_N is used to latch an internal data register with data provided via the data bus lines D_[7:0]. In Motorola Bus Mode (R/W_N), this R/W_N input is used to distinguish between read or write during a microprocessor access. (TTL Input, Pull up) DMA Acknowledge Reserved for future internal HDLC controller. If unused, this pin should be left unconnected (TTL Input) Reset. This active high signal initializes the microprocessor interface, configuration, routing and parallel access registers. (CMOS Input) Crystal Clock Input. This pin is a CMOS level input of either 2.048, 4.096, 8.192, 16.384, 32.768 or 65.536 MHz. A crystal of 16.384 MHz from X_IN to X_OUT may also be used. (CMOS Output) Crystal Clock Output. (TTL Bi-Directional) Internal Master PLL (REF_8K_3). If configuration register bit C_43=0, this pin is a Local 8 KHz Reference 3 Input. External Master PLL (REF_8K_OUT). If configuration register bit C_43=1, this pin is an 8 KHz Reference Output. (TTL Input) Internal Master PLL (REF_8K_2). If configuration register bit C_43=0, this pin is a Local 8 KHz Reference 2 Input. External Master PLL (CLK_IN). If configuration register bit C_43=1, this is a clock input from external master PLL. (TTL Input) Local 8 KHz Reference 1 Input. (TTL Input) Local 8 KHz Reference 0 Input. (TTL Input, Pull Up) Local Bus Serial Input Data Streams. This pin can be programmed to 2.048, 4.096 or 8.192 Mb/s data rates. (TTL Input, Pull Up) Message Channel Transmit Data. This pin is for the SCbus Message channel transmit data input line. (TTL Input) NAND Gate Test Mode Enable. When in test mode (TEST=1) each pin except VDD/VSS/X_OUT is nanded with the preceding pin and output at both DRQ_R and DRQ_T pins. (TTL Bi-directional) Interrupt Request 1. Reserved for future internal HDLC controller. If unused, this pin should be left unconnected. (TTL Bi-directional) Interrupt Request 0. This pin will be asserted (controlled by C_[55:53]) if either SCbus Error, SCbus CLKFAIL, Frame Boundary or Internal Master PLL Error and INT_0 unmasked (C_53 = 1).
I
19
I
20
I I I O I O I
21 96 2 1 7
6
I I I I I I/O I/O
5 4 95,94,92,91 9 98 15 14
2000 Sep 07
10
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
Pin Description (continued)
Pin Name DRQ_R or TEST_OUT_0 DRQ_T or TEST_OUT_1 SCLKX2N SCLKX2NA SCLK Input/Output O Pin Number 99 Pin Description
SC4000
(TTL Output) Receive DMA Request. This pin is reserved for a future internal HDLC controller. Otherwise, in Test Mode (TEST=1), this is a NANDed gate test chain 0 output. (TTL Output) Transmit DMA Request. This pin is reserved for a future internal HDLC controller. Otherwise, in Test Mode (TEST=1), this is a NANDed gate test chain 1 output. (SCbus Bi-directional) SCbus System clock x 2. (SCbus Bi-directional) SCbus Alternate System clock x 2. (SCbus Bi-directional) SCbus System clock. This can be programmed to either 2.048, 4.096 or 8.192 MHz. Set C_0 = 1 to enable the SCLK output driver as master mode. Set C_0 = 0 to disable the SCLK output driver as slave mode. (SCbus Bi-directional) SCbus Alternate System clock. (SCbus Bi-directional) SCbus 8 KHz Reference. If C_46 = 1, the SREF_8K output is enabled at SCbus If C_46 = 0, the SREF_8K output is disabled at SCbus (SCbus Bi-directional) SCbus 8 KHz Alternate Reference. (SCbus Bi-directional) SCbus 8 KHz Frame Synchronization signal. Set C_0 = 1 to enable the FSYNCN output driver as master mode. Set C_0 = 0 to disable the FSYNCN output driver as slave mode. (SCbus Bi-directional) SCbus 8 KHz Alternate Frame Synchronization signal. (SCbus Bi-directional) SCbus System Clock Fail signal. (SCbus Bi-directional) SCbus Alternate System Clock Fail signal. (SCbus Bi-directional) These are SCbus Serial Data Streams can be programmed to 2.048, 4.096 or 8.192 Mb/s data rates.
O
100
I/O I/O I/O
46 47 49
SCLKA SREF_8K
I/O I/O
50 51
SREF_8KA FSYNCN
I/O I/O
52 54
FSYNCNA CLKFAIL CLKFAILA SD_[0:15]
I/O I/O I/O I/O
55 56 58 59,60,62,63, 64,66,67,68, 70,71,72,74, 75,76,77,79 80 81 83 84 90,88,87,86 11 10 8,13,29,37,48, 61,65,78,85,89 3,18,23,33,41, 45,53,57,69,73, 82,93,97
MC MCA L_CLK L_FS S0_[3:0] MC_CLK RXD VDD VSS
I/O I/O I/O I/O I/O I/O I/O Power Power
(SCbus Bi-directional Open Collector) SCbus Message Channel. (SCbus Bi-directional Open Collector) SCbus Alternate Message Channel. (TTL Bi-directional) Local bus Clock Output. It can be programmed to: 2.048, 4.096 or 8.192 MHz if set C_28 = 0. 4.096, 8.192 or 16.384 MHz if set C_28 = 1. (TTL Bi-directional) Local bus 8 KHz Frame Synchronization Output. (TTL Bi-directional) Local Bus Serial Output Data Streams. It can be programmed to 2.048, 4.096 or 8.192 Mb/s data rates. (TTL Bi-directional) Message Channel Data Clock. This pin is a 2.048 MHz output. The clock duty cycle can be programmed by C_14 bit. (TTL Bi-directional) Message Channel Receive Data. This pin is for the SCbus message channel receive data output line. +5 Volt Power Supply. Ground.
Note: In Test mode (TEST=1), every pin except VDD/VSS/X_OUT/DRQ_R/DRQ_T is configured as input.
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Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
DEVICE OVERVIEW The SC4000 Universal Timeslot Interchange is designed to provide the hardware interface to the SCbus. Its primary function is exchanging digital data between the Local bus serial port and the SCbus serial port. A microprocessor interface allows the host controller to specify the timeslots and serial lines for this exchange. Both the SCbus and the Local bus can be programmed to operate at either 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s. As shown in Figure 1 , the destination routing memory defines the Local Bus to SCbus switch connection. There are 128 destination routing memory locations -- one for each Local Bus input channel. The data stored in the destination routing memory selects the timeslot and SCbus serial port connection for the Local Bus input channel. The source routing memory defines the SCbus to Local Bus switch connection. There are 128 source routing memory locations -- one for each Local Bus output channel.
SC4000
The data stored in the source routing memory selects the time slot and SCbus serial port connection for the Local Bus output channel.
Local Bus Channels to Serial Ports SI and SO Time Slot Assignments
Framing mode 2.048 Mb/s 4.096Mb/s 8.192 Mb/s SI_0 and SO_0 ch[0:31] -> ts[0:31] ch[0:63] -> ts[0:63] ch[0:127] -> ts[0:127] SI_1 and SO_1 ch[32:63] -> ts[0:31] ch[64:127] -> ts[0:63] SI_2 and SO_2 ch[64:95] -> ts[0:31] SI_3 and SO_3 ch[96:127] -> ts[0:31]
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Preliminary specification
Universal Timeslot Interchange
Writing to the routing memory is synchronized with SCbus timing. So routing information can be changed only on time slot boundaries. All input data is buffered in holding registers. The entire holding register is transferred to the output registers on a frame boundary basis. All frame-bounded time slots incur a one frame delay as they pass through the switch. Switching data in this fashion supports time slot bundling. The SO outputs are tri-state controlled on time slot boundaries by the Source Routing Memory Switch Output Enable Bit. This allows SO outputs from multiple devices to be connected to a common line. The data sample position of both the SCbus and the Local bus can be selected for either 50% or 75% of the bit cell. In addition to switching local bus serial data to and from the SCbus, the SC4000 provides a means of switching parallel data through the microprocessor interface to the SCbus. A frame boundary interrupt helps control the timing of parallel data accesses. Direct reading and writing of parallel access register contents makes for an efficient data transfer. When using direct access, the controlling processor places the address of the target channel on the address bus. In this way, data can be read or written in a single cycle. To avoid data corruption, the application should not access the channel for a time period defined as four clocks before and four clocks after the frame boundary. The Source Routing Memory Local Connect Enable mode allows the switching of any destination channel to
SC4000
any source channel without SCbus intervention. This mode accommodates either serial or parallel data transfer. Since data passes through the switch twice in this mode, there is a two-frame delay from input to output. Diagnostic mode electrically disconnects the SC4000 from the SCbus but allows access through the local bus. This mode is particularly useful for running board diagnostics without upsetting the SCbus. A Master Clock source is required to run this mode. The SC4000 pinout anticipates a future version of the chip that includes an internal HDLC controller for the message channel. To remain compatible with this and other subsequent versions of the SC4000, applications must write 0 to all "Reserved (read only)" configuration registers.
Figure 1. Destination and Source Switch Function Block
1 OF 128 DESTINATION SWITCH
SI_[3:0]
INPUT HOLDING REGISTER O
OUTPUT HOLDING REGISTER TIMESLOT & PORT OUTPUT ENABLE PARALLEL ACCESS ENABLE LOCAL CONNECT BUS
SD_[15:0]
D_[7:0] W/R_N
I PARALLEL ACCESS REGISTER
DESTINATION ROUTING MEMORY
SOURCE ROUTING MEMORY INTERNAL PARALLEL ACCESS READ
1 OF 128 SOURCE SWITCH
TIMESLOT, OUTPUT HOLDING REGISTER OUTPUT ENABLE INPUT HOLDING REGISTER CONNECT ENABLE PORT AND LOCAL
SO_[3:0]
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Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
FUNCTION DESCRIPTION Switching The SC4000 allows data switching through the microprocessor interface in any of the following three directions: * From any local bus serial channel (SI) or parallel data bus D_[7:0] input to any SCbus channel (SD) output * From any SCbus channel (SD) input to any output of the local bus serial channel (SO) or parallel data bus D_[7:0] * From any of local bus serial channel (SI) or parallel data bus D_[7:0] input directly through an internal local connect bus to any local bus serial channel (SO) output As shown in Figure 1, each input SI and output SO channel is mapped to one of 128 unique locations in the destination routing memory and source routing memory, respectively. So data stored in the destination or source routing memory selects the timeslot and serial port of the SCbus. All data is buffered through the input holding register, output holding register or parallel access register for a switching matrix with one frame delay. PLL Timing and Clock Control The SC4000 provides the option of using the internal master PLL (C_43 = 0) or an external master PLL (C_43 = 1). As shown in Figure 2, the internal master PLL generates a clock that is frequency-locked to an 8 KHz reference input of either SREF_8K or REF_8K[3:0]. When the SC4000 is enabled as SCbus master (C_0 =1), a state machine inside the SC4000 uses this clock to generate
SC4000
SCLK, SCLKX2N and a "free-running" FSYNCN signal based on the speed of the SCbus and the clock frequency. The internal master PLL runs free when: * Put into free run mode (ignoring reference input changes) by control C_[42:40] * The 8 KHz reference input is static "1" or "0" * The input of X_IN is less than 65.536 MHz. The internal master PLL can also generate an interrupt if it cannot lock the selected 8 KHz reference input.
Figure 2. Internal Master PLL (C_43 = 0) Function Block
C_0, C_3, C_[23:22] EXTERNAL CRYSTAL or OSC C_[10:8], C_[5:4] X_IN X_OUT SCLKX2N SCLKX2NA 46, 47 FSYNCN FSYNCNA SCbus Clock Master PLL Programmable Divider 54, 55 SCLK SCLKA 49, 50 C_2 To Internal Watchdogs and SCbus Error Detectors
C_[42:40]
2
1
65.536 MHz REF_8K_[3:0] 4, 5, 6, 7 Master PLL Reference 8 K Select
C_[45:44]
Primary or Alternate Select
SCbus SREF_8K Source Select C_3, C_23, C_46
SREF_8K SREF_8KA 51, 52
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Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
Figure 3 shows an external master PLL implementation. The SC4000 provides the 8 KHz reference output signal REF_8K_OUT (pin 7) to the external PLL. This 8 KHz reference signal is sourced from either REF_8K[1:0] or SREF_8K. The output of the external PLL is then routed back to the SC4000 via CLK_IN (pin 6). The master clock input (CLK_IN) frequency select at C_[10:8] would then be programmed for the external PLL frequency. As shown in Figure 4, the SC4000 also provides an internal clock PLL and local bus PLL timing control circuitry for both SCbus master and slave operations. The internal clock PLL is used to create the 4.096 or 8.192 MHz timing slaved to the SCbus when the local bus is running faster than the SCbus (i.e., 2.048 MHz at SCbus, 8.096 MHz at local bus). If the SCbus is faster or equal to the local bus, then the SCbus clocks serve as the internal clock and use to create the local bus clocks as well as message channel clock. The local bus clock PLL is used to create a 2.048 MHz L_CLK when: * Local bus framing mode C_[7:6] is set to 2.048 Mb/s * A 65.536 MHz clock is supplied on X_IN * The C_29 bit is set to one. If SCLK stops transitionally such as during a clock fail condition (CLKFAIL = 1), then the local bus clock PLL runs free to generate L_CLK clock. In addition, the local bus SO lines are tri-stated so that the network interface can continue to run. Interrupts Control The SC4000 can interrupt the host CPU with the interrupt request signal INT_0
SC4000
(pin 14). This signal is configured and unmasked by configuration register bits C_55, C_54 and C_53. The interrupt sources are: * C_56 SCbus CLKFAIL * C_57 Frame Boundary * C_58 Internal Master PLL Error * C_59 SCbus Error Indicator (logical "OR" of C_[67:64], C_[74:72], and C_[83:80]) The interrupts are structured this way to improve performance by allowing a single read operation (of configuration register byte 7) to determine whether the SC4000 is the source of the interrupt. Each of the SC4000 interrupt sources can be individually masked.
Figure 3. External Master PLL (C_43 = 1) Function Block
C_0, C_3, C_[23:22] REF_8K_OUT SCLKX2N SCLKX2NA 46, 47 FSYNCN FSYNCNA Programmable REF_8K_[1:0] 4, 5 Master PLL Reference 8 K Select C_2 To Internal Watchdogs and SCbus Error Detectors Divider 54, 55 SCLK SCLKA 49, 50
External CLK_IN PLL 6 7
C_[10:8], C_[5:4]
C_[42:40]
C_[45:44]
Primary or Alternate Select
SCbus SREF_8K Source Select C_3, C_23, C_46
SREF_8K SREF_8KA 51, 52
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Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
Figure 4. Internal PLL and Local Bus PLL Timing Function Block
SC4000
X_IN 2 SCLK 49 SCLKA 50
65.536 MHz
Internal Clock PLL Primary or Alternate Select Internal Timing
Local Bus Clock PLL
1 L_CLK 83 0
Control State Machine C_[7:6]=0X (2.048 Mb/s) C_29=1
SCLKX2N 46 SCLKX2NA 47 2.048 MHz FSYNCN 54 FSYNCNA 55 C_2 Primary or Alternate Select C_[7:6], C_[5:4] MC_CLK 11 Primary or Alternate Select L_FS 84
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Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
CLKFAIL Timing and Control When an SC4000 is enabled to be clock master (C_0 = 1), the chip drives clock and frame sync signals to the SCbus and pulls the CLKFAIL line low. If the SC4000 is then disabled as clock master, the internal state machine waits for the next frame boundary and then stops driving clock and frame sync signals. Instead, it drives the CLKFAIL line high for one clock before tri-stating it (CLKFAIL is pulled up with 4.7K on every board). An "armed" clock master (C_1 = 1) contains logic that monitors the CLKFAIL line (C_51 must be set). If CLKFAIL is sampled high for two consecutive clock periods, then the C_0 bit is automatically set; the armed master then begins driving clock and frame sync signals and pulls CLKFAIL low. Since the internal state machine was using the clock and frame sync signals driven by the previous master, the new master takes over without any framing error. It is as if one clock period had been stretched, as shown in Figure 14. Message Channel Interface The SC4000 is designed for use with an HDLC controller to implement the message channel interface. The interface between an HDLC controller and SC4000 consists of the 2.048 MHz MC_CLK (pin 11), TXD_0 (pin 9) and RXD (pin 10) lines. Data read from the SCbus MC (pin 80) line is passed straight through the SC4000 to the RXD output. Data read from TXD_0 can be passed straight through the SC4000 to the MC output, or be buffered internally through a clocked register. Buffering output data is controlled by C_12. When the Message
SC4000
Channel is Disabled (C_15 = 1), TXD_0 is looped back to the RXD to allow diagnostics to be run on the HDLC controller. Operation Mode and Configuration Register Setup The SC4000 can be configured to function in five different modes shown in the tables below: * SCbus Clock Slave (Table 1) * SCbus Clock Master (Table 2) * SCbus Armed Clock Master (Table 3) * MVIP Clock Master (Table 4) * MVIP Clock Slave (Table 5) Table 6 shows signals that are cross referenced by SCbus and MVIP.
Table 1. Configuration Register Setup for SCbus Clock Slave
Operation Mode
SCbus Slave
Conguration Register Bits Setup
C_0 = 0 C_1 = 0 C_2
Function Description
SCbus clock master disabled (Default) SCbus clock master disarmed (Default) SCbus Primary or Alternate Select 0: Primary SCbus signals selected (Default) 1: Alternate SCbus signals selected Diagnostic mode disabled (Note) SCbus Framing mode to select one of the following rate: 0X = 2.048 Mb/s, 256 Bits/Frame, 32 Timeslots/Frame (Default) 10 = 4.096 Mb/s, 512 Bits/Frame, 64 Timeslots/Frame 11 = 8.192 Mb/s, 1024 Bits/Frame, 128 Timeslots/Frame Local bus Framing mode to select one of the following rate: 0X = 2.048 Mb/s, 256 Bits/Frame, 32 Timeslots/Frame (Default) 10 = 4.096 Mb/s, 512 Bits/Frame, 64 Timeslots/Frame 11 = 8.192 Mb/s, 1024 Bits/Frame, 128 Timeslots/Frame
C_3 = 0 C_[5:4]
C_[7:6]
Note: Default of all configuration register bits except C_3 are 0
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Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
Table 2. Configuration Register Setup for SCbus Clock Master
Operation Mode SCbus Master Conguration Register Bits Setup C_0 = 1 C_1 = 0 C_2 Function Description SCbus clock master enabled SCbus clock master disarmed (Default) SCbus Primary or Alternate Select 0: Primary SCbus signals selected (Default) 1: Alternate SCbus signals selected Diagnostic mode disabled SCbus Framing mode to select one of the following rate: 0X = 2.048 Mb/s, 256 Bits/Frame, 32 Timeslots/Frame (Default) 10 = 4.096 Mb/s, 512 Bits/Frame, 64 Timeslots/Frame 11 = 8.192 Mb/s, 1024 Bits/Frame, 128 Timeslots/Frame Local bus Framing mode to select one of the following rate: 0X = 2.048 Mb/s, 256 Bits/Frame, 32 Timeslots/Frame (Default) 10 = 4.096 Mb/s, 512 Bits/Frame, 64 Timeslots/Frame 11 = 8.192 Mb/s, 1024 Bits/Frame, 128 Timeslots/Frame Master clock input frequency select: 000 = 2.048 MHz (Default), 001 = 4.096 MHz, 010 = 8.192 MHz, 011 = 16.384 MHz, 100 = 32.768 MHz, 101= 65.536 MHz, 11X =Reserved SCbus FSYNCN rate to select one SCLK period (Default) SCbus SCLKX2N and SCLKX2NA output enable control 0: SCbus SCLKX2N and SCLKX2NA output enabled (Default) 1: SCbus SCLKX2N and SCLKX2NA output disabled SCbus Alternate signals output enable control 0: SCbus Alternate signals output disabled (Default) 1: SCbus Alternate signals output enabled
SC4000
C_3 = 0 C_[5:4]
C_[7:6]
C_[10:8]
C_21 = 0 C_22
C_23
C_[43:40] (Internal/External Master PLL reference 8K select)
Internal/External Master PLL reference select: If C_43 = 0 select the reference for the internal master PLL from C_[42:40]: 000 = Free-run (Default), 001/010 = Free-run, 011 = SREF_8K/SREF_8KA, 100 = REF_8K_0, 101 = REF_8K_1, 110 = REF_8K_2, 111 = REF_8K_3 (see Figure 2) If C_43 = 1 select the reference for the external master PLL (output on REF_8K_OUT pin 7) from C_[42:40]: 000 = Free-run (driven high) (Default), 001/010 = Free-run (driven high), 011 = SREF_8K/SREF_8KA, 100 = REF_8K_0, 101 = REF_8K_1, 110/111 = Tri-state (Z) (see Figure 3)
C_51 = 1
SCbus CLKFAIL latch debounce enabled
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Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
Table 3. Configuration Register Setup for SCbus Armed Clock Master
Operation Mode SCbus Armed Master Conguration Register Bits Setup C_0 = 0 C_1 = 1 C_2 Function Description SCbus clock master disabled initially
SC4000
SCbus clock master armed. When CLKFAIL goes high, C_0 bit will be automatically set and SC4000 becomes clock master SCbus Primary or Alternate Select 0: Primary SCbus signals selected (Default) 1: Alternate SCbus signals selected Diagnostic mode disabled SCbus Framing mode to select one of the following rate: 0X = 2.048 Mb/s, 256 Bits/Frame, 32 Timeslots/Frame (Default) 10 = 4.096 Mb/s, 512 Bits/Frame, 64 Timeslots/Frame 11 = 8.192 Mb/s, 1024 Bits/Frame, 128 Timeslots/Frame Local bus Framing mode to select one of the following rate: 0X = 2.048 Mb/s, 256 Bits/Frame, 32 Timeslots/Frame (Default) 10 = 4.096 Mb/s, 512 Bits/Frame, 64 Timeslots/Frame 11 = 8.192 Mb/s, 1024 Bits/Frame, 128 Timeslots/Frame Master clock input frequency select: 000 = 2.048 MHz (Default), 001 = 4.096 MHz, 010 = 8.192 MHz, 011 = 16.384 MHz, 100 = 32.768 MHz, 101= 65.536 MHz, 11X =Reserved SCbus FSYNCN rate to select one SCLK period (Default) SCbus SCLKX2N and SCLKX2NA output enable control 0: SCbus SCLKX2N and SCLKX2NA output enabled (Default) 1: SCbus SCLKX2N and SCLKX2NA output disabled SCbus Alternate signals output enable control 0: SCbus Alternate signals output disabled (Default) 1: SCbus Alternate signals output enabled Internal/External Master PLL reference select: If C_43 = 0 select the reference for the internal master PLL from C_[42:40]: 000 = Free-run (Default), 001/010 = Free-run, 011 = SREF_8K/SREF_8KA, 100 = REF_8K_0, 101 = REF_8K_1, 110 = REF_8K_2, 111 = REF_8K_3 (see Figure 2) If C_43 = 1 select the reference for the external master PLL (output on REF_8K_OUT pin 7) from C_[42:40]: 000 = Free-run (driven high) (Default), 001/010 = Free-run (driven high), 011 = SREF_8K/SREF_8KA, 100 = REF_8K_0, 101 = REF_8K_1, 110/111 = Tri-state (Z) (see Figure 3)
C_3 = 0 C_[5:4]
C_[7:6]
C_[10:8]
C_21 = 0 C_22
C_23
C_[43:40] (Internal/External Master PLL reference 8K select)
C_51 = 1
SCbus CLKFAIL latch debounce enabled
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Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
Table 4. Configuration Register Setup for MVIP Clock Master
Operation Mode MVIP Master Conguration Register Bits Setup C_0 = 1 C_1 = 0 C_2 = 0 C_3 = 0 C_[5:4] =00 C_[7:6] Function Description MVIP clock master enabled MVIP clock master disarmed (Default) Primary SCbus signals selected (Default) Diagnostic mode disabled (Note 1) MVIP Framing mode to select only one rate: 0X = 2.048 Mb/s, 256 Bits/Frame, 32 Timeslots/Frame (Default) Local bus Framing mode to select one of the following rate: 0X = 2.048 Mb/s, 256 Bits/Frame, 32 Timeslots/Frame (Default) 10 = 4.096 Mb/s, 512 Bits/Frame, 64 Timeslots/Frame 11 = 8.192 Mb/s, 1024 Bits/Frame, 128 Timeslots/Frame Master clock input frequency select: 000 = 2.048 MHz (Default), 001 = 4.096 MHz, 010 = 8.192 MHz, 011 = 16.384 MHz, 100 = 32.768 MHz, 101= 65.536 MHz, 11X =Reserved MVIP F0/ rate to select one C4/ period MVIP C4/ output enabled (Default) SCbus Alternate signals output disabled (Default)
SC4000
C_[10:8]
C_21 = 1 C_22 = 0 C_23 =0 C_[43:40] (Internal/External Master PLL reference 8K select)
Internal/External Master PLL reference select: If C_43 = 0 select the reference for the internal master PLL from C_[42:40]: 000 = Free-run (Default), 001/010 = Free-run, 011 = SEC_8K, 100 = REF_8K_0, 101 = REF_8K_1, 110 = REF_8K_2, 111 = REF_8K_3 (see Figure 2) If C_43 = 1 select the reference for the external master PLL (output on REF_8K_OUT pin 7) from C_[42:40]: 000 = Free-run (driven high) (Default), 001/010 = Free-run (driven high), 011 = SEC_8K, 100 = REF_8K_0, 101 = REF_8K_1, 110/111 = Tri-state (Z) (see Figure 3)
Table 5. Configuration Register Setup for MVIP Clock Slave
Operation Mode MVIP Slave Conguration Register Bits Setup C_0 = 0 C_1 = 0 C_2 = 0 C_3 = 0 C_[5:4] = 00 C_[7:6] Function Description MVIP clock master disabled (Default) MVIP clock master disarmed (Default) Primary SCbus signals selected (Default) Diagnostic mode disabled MVIP Framing mode to select only one rate: 0X = 2.048 Mb/s, 256 Bits/Frame, 32 Timeslots/Frame (Default) Local bus Framing mode to select one of the following rate: 0X = 2.048 Mb/s, 256 Bits/Frame, 32 Timeslots/Frame (Default) 10 = 4.096 Mb/s, 512 Bits/Frame, 64 Timeslots/Frame 11 = 8.192 Mb/s, 1024 Bits/Frame, 128 Timeslots/Frame
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Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
Table 6. SCbus/MVIP Signals Cross Reference
SCbus 26-Pin Connector 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 SCbus Signal SCLKX2N GND SCLK SREF_8K FSYNCN CLKFAIL SD_0 GND SD_1 SD_2 SD_3 SD_4 SD_5 SD_6 GND SD_7 SD_8 SD_9 SD_10 SD_11 GND SD_12 SD_13 SD_14 SD_15 MC MVIP Signal C4/ GND C2 SEC_8K F0/ N/A DSi0 GND DSo0 DSi1 DSo1 DSi2 DSo2 DSi3 GND DSo3 DSi4 DSo4 DSi5 DSo5 GND DSi6 DSo6 DSi7 DSo7 N/A MVIP 40-Pin Connector 31 30, 32 35 37 33 N/A 8 34 7 10 9 12 11 14 36 13 16 15 18 17 38 20 19 22 21 N/A
SC4000
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Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
Register Access Schemes The SC4000 features two address access schemes. One is an indirect access scheme (C_11 = 0) to reduce the number of pins required for the microprocessor address bus interface from nine to two (A_[1:0]), as shown in Figure 5. The other is a combination of both indirect and direct parallel access schemes (C_11 = 1). Using the combination requires
SC4000
that all nine microprocessor address pins (A_[8:0]) be used, as shown in Figure 6.
Figure 5. Using Two Pins A_[1:0] for Address Bus Interface Scheme (C_11 = 0)
Address
03h 02h 01h 00h
Data
High Byte Data Register (HBDR) Low Byte Data Register (LBDR) Internal Address Register (IAR) Command/Status Register (CSR)
FFh - E0h DFh - C0h BFh - A0h 9Fh - 80h 7Fh - 0Dh 0Ch - 00h
Source Parallel Access (31 - 0) Destination Parallel Access (31 - 0) Source Routing Memory (31 - 0) Destination Routing Memory (31 - 0) Reserved Configuration Register (12 - 0)
A_[1:0]
D_[7:0]
Note:See bit 5 and 4 of CSR to select the bank of channels
Microprocessor
Figure 6. Using Nine Pins A_[8:0] for Address Bus Interface Scheme (C_11 = 1)
Address
1FFh - 180h 17Fh - 100h FFh - 04h 03h 02h 01h 00h
Data
Source Parallel Access (127 - 0) Destination Parallel Access (127 - 0) Reserved High Byte Data Register (HBDR) Low Byte Data Register (LBDR) Internal Address Register (IAR) Command/Status Register (CSR) FF - E0 DF - C0 BF - A0 9F - 80 7F - 0D 0C - 00 A_[8:0] D_[7:0] Source Parallel Access (31 - 0) Destination Parallel Access (31 - 0) Source Routing Memory (31 - 0) Destination Routing Memory (31 - 0) Reserved Configuration Register (12 - 0)
Note:See bit 5 and 4 of CSR to select the bank of channels
Microprocessor
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Preliminary specification
Universal Timeslot Interchange
MICROPROCESSOR INTERFACE I/O Address Map With Direct R/W to Parallel Access Registers Disabled (C_11=0) (default) Busy (D_0) (Read Only) This bit is set ("1") when a command that requires synchronization with the SC4000's internal state machine has been initiated. This bit clears ("0") when the command is completed. The following commands require synchronization: * Destination Routing Memory Write command * Source Routing Memory Write command * Indirect Parallel Access Destination Write command * Indirect Parallel Access Source Read command Read (D_1) (Write only) Setting this bit ("1") initiates a read of the register pointed to by the Internal Address Register. When the Busy bit is clear ("0"), the contents of the register to be read are available by reading the Low byte & HighByte Data register. It is not necessary to clear ("0") this bit after it has been set ("1"). Note: Set this bit for an Indirect Parallel Access Source Read (this is the only "READ" requiring synchronization). For reads which do not require synchronization, the data registers can be read immediately after writing the internal address register. Write (D_2) (Write only) Setting this bit ("1") initiates a write to the register selected by the Internal Address Register. When the Busy bit is clear ("0"), the contents of the target register have been updated using the data stored in the Low Byte & High Byte Data Register. It is not necessary to clear ("0") this bit after it has been set ("1"). Terminate (D_3) (Read/Write) Setting this bit ("1") terminates a command that requires synchronization with the SC4000's internal state machine. This is necessary to complete a command when the SC4000's internal
SC4000
state machine has stopped running (no SCLK). The command in process is completed asynchronously and the Busy bit is cleared. It is necessary to clear ("0") this bit after it has been set ("1"). Note : A new command (Read or Write) should not be issued until after the Terminate bit is cleared ("0"). Channel Bank Select Register [1:0] (D_[5:4]) (Read/Write) This field determines the bank of channels that a command will affect. The Channel Bank Select Register field is combined with the Internal Address Register to provide access to the channel specific registers (routing and parallel access). D_[5:4]) selects the bank of channels to be accessed. This field is cleared ("00") on reset. D_[5:4] = 00 -> Ch. 0 - 31 D_[5:4] = 01 -> Ch.32 - 63 D_[5:4] = 10 -> Ch.64 - 95 D_[5:4] = 11 -> Ch.96 - 127 Channel Bank Select Register Enable (D_6) (Write only) Writing to the command register with this bit set ("1") enables the Channel bank select field to be changed. Writing to the command register with this bit cleared ("0") causes the Channel Bank Select Register field to retain its previous value. Note 1:The Channel Bank Select Register may be changed during a write cycle which also initiates a Read or Write command. The Read or Write command affects the register pointed to by the new value written into the Channel Bank Select Register. Note 2:The Channel Bank Select Register should not be changed if the microprocessor interface is busy. Note 3:The Channel Bank Select Register should not be changed during a write cycle that either sets (0->1) or clears (1->0) the Terminate command.
A_[1:0]
3h 2h 1h 0h
REGISTER
High Byte Data Register (HBDR) Low Byte Data Register (LBDR) Internal Address Register (IAR) Command / Status Register
With direct R/W to Parallel Access Register Enable (C_11=1 )
A_[8:0]
1FFh:180h 17Fh:100h 0FFh:004h 003h 002h 001h 000h
REGISTER
Source Parallel Access Register Ch. 127:0 Destination Parallel Access Register Ch. 127:0 Reserved High Byte Data Register (HBDR) Low Byte Data Register (LBDR) Internal Address Register (IAR) Command / Status Register
Command / Status Register (Address = 0h)
D_[7:0]
0 1 2 3 [5:4] 6 7
Definition
Busy (Read only) Read Command (Write only) Write Command (Write only) Terminate Command (Read/Write) Channel Bank Select Register [1:0] (Read/Write) Channel Bank Select Register Enable (Write only) Reset (Read/Write)
Note: Setting more than one command (Read, Write, Terminate or Reset) during an access to the Command/Status register is not recommended.
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Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
Reset (D_7) (Read/Write) Setting this bit ("1") puts the SC4000 in reset and initializes the Configuration, Routing and Parallel Access Registers. This command is analogous to the function of the RESET pin. Clearing this bit ("0") returns the SC4000 to normal operation, ready for configuration. Internal Address Registerr (Address = 01h) Internal Address Register Map
SC4000
Low Byte Data Register (Address = 02h)
IAR_ [7:0]
FFh:80h
Register
Channel Specific Registers
IAR_ [7:0]
FFh:E0h
Register
Source Parallel Access Destination Parallel Access Source Routing Memory Destination Routing Memory
D_[7:0]
7:0
Definition
Low byte Data Register (LBDR_[7:0])
High Byte Data Register (Address = 03h)
DFh:C0h
D_[7:0]
7:0
Definition
High byte Data Register (HBDR_[7:0])
D_[7:0]
7:0
Definition
Internal Address Register (IAR_[7:0])
BFh:A0h
9Fh:80h
7Fh:0Dh 0Ch:00h
Reserved Configuration Registers
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Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
Channel Specific Registers The Channel Specific Registers are divided into four groups. A group is selected by bits 5 through 7 of theinternal address register. IAR_[7:5] 100 -> Destination Routing Memory 101 -> Source Routing Memory 110 -> Destination Parallel Access 111 -> Source Parallel Access Channel Specific Registers Map
SC4000
Channels within these groups are selected by bits 4 through 0 (IAR_[4:0]) of the Internal Address Register and bits 1 and 0 (D_[5:4] Command/Status Register) of the Channel Bank Select Register (CBSR)
D_[5:4] of Command/Status Register (D_6 = 1) IAR[7:0]
IAR_[7:5] FFh - E0h Source Parallel Access IAR_[4:0] = 1Fh IAR_[4:0] = 1Eh . . IAR_[4:0] = 01h IAR_[4:0] = 00h IAR_[7:5] DFh - C0h Destination Parallel Access IAR_[4:0] = 1Fh IAR_[4:0] = 1Eh . . IAR_[4:0] = 01h IAR_[4:0] = 00h IAR_[7:5] BFh - A0h Source Routing Memory IAR_[4:0] = 1Fh IAR_[4:0] = 1Eh . . IAR_[4:0] = 01h IAR_[4:0] = 00h IAR_[7:5] 9Fh - 80h Destination Routing Memory IAR_[4:0] = 1Fh IAR_[4:0] = 1Eh . . IAR_[4:0] = 01h IAR_[4:0] = 00h
CBSR_[1:0] = 00
Ch. 31 Ch. 30 . . Ch. 1 Ch. 0 Ch. 31 Ch. 30 . . Ch. 1 Ch. 0 Ch. 31 Ch. 30 . . Ch. 1 Ch. 0 Ch. 31 Ch. 30 . . Ch. 1 Ch. 0
CBSR_[1:0] = 01
Ch. 63 Ch. 62 . . Ch. 33 Ch. 32 Ch. 63 Ch. 62 . . Ch. 33 Ch. 32 Ch. 63 Ch. 62 . . Ch. 33 Ch. 32 Ch. 63 Ch. 62 . . Ch. 33 Ch. 32
CBSR_[1:0] = 10
Ch. 95 Ch. 94 . . Ch. 65 Ch. 64 Ch. 95 Ch. 94 . . Ch. 65 Ch. 64 Ch. 95 Ch. 94 . . Ch. 65 Ch. 64 Ch. 95 Ch. 94 . . Ch. 65 Ch. 64
CBSR_[1:0] = 11
Ch. 127 Ch. 126 . . Ch. 97 Ch. 96 Ch. 127 Ch. 126 . . Ch. 97 Ch. 96 Ch. 127 Ch. 126 . . Ch. 97 Ch. 96 Ch. 127 Ch. 126 . . Ch. 97 Ch. 96
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Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
Destination Routing Memory--Low Byte 0 -> Output Disabled (Default) 1 -> Output Enabled Source Routing Memory-- Low Byte 2h -> SCbus SD_2 . . Eh -> SCbus SD_14 Fh -> SCbus SD_15
SC4000
LBDR_[7:0]
[6:0] 7
Definition
Time-slot Select [6:0] Reserved
LBDR_[7:0]
[6:0] 7
Definition
Time-Slot/Channel Select [6:0] Reserved
Time-Slot Select [6:0] (Read/write) This field selects the SCbus Time-Slot that a Destination Channel is routed to. 00h -> SCbus Time-Slot 0 (Default) 01h -> SCbus Time-Slot 1 02h -> SCbus Time-Slot 2 . . 7Eh -> SCbus Time-Slot 126 7Fh -> SCbus Time-Slot 127 Destination Routing Memory-- High Byte
If Local Connect is enabled this field is don't care. Local Connect Enable (Read/Write) This bit enables the Local Connection of a Destination Channel to a Source Channel. 0 -> Local Connect Disabled (Default) 1 -> Local Connect Enabled Switch Output Enable (Read/Write) This bit enables the Switch Output to the Local Bus. 0 -> Output Disabled (Default) 1 -> Output Enabled Parallel Access The parallel access channels can be accessed two ways: Indirect and Direct. Destination Parallel Access
Time-Slot/Channel Select [6:0] (Read/Write) If Local Connect is disabled (default) this field selects the SCbus Time-Slot that is routed to a Source Channel. 00h -> SCbus Time-Slot 0 (Default) 01h -> SCbus Time-Slot 1 02h -> SCbus Time-Slot 2 . . 7Eh -> SCbus Time-Slot 126 7Fh -> SCbus Time-Slot 127
HBDR_[7:0]
[3:0] [5:4] 6 7
Definition
Port Select [3:0] Reserved Parallel Access Enable Switch Output Enable
If Local Connect is enabled this field selects the Destination Channel that is routed to a Source Channel. 00h -> Destination Channel 0 (Default) 01h -> Destination Channel 1 02h -> Destination Channel 2 . . 7Eh -> Destination Channel 126 7Fh -> Destination Channel 127 Source Routing Memory--High byte
Port Select [3:0] (Read/Write) This field selects the SCbus Port that a Destination Channel is routed to. 0h -> SCbus SD_0 (Default) 1h -> SCbus SD_1 2h -> SCbus SD_2 . . Eh -> SCbus SD_14
LBDR_[7:0]
[7:0]
Definition
Serial Data Bit [1:8]
Serial Data [1:8] (Read/Write) This register contains the byte to be transmitted when Destination Routing Memory Parallel Access is enabled Note:When converted from parallel to serial, bit 1 is transmitted first. Note This register is cleared ("00") : on Reset. Source Parallel Access
HDBR_[7:0]
[3:0]
Definition
Port Select [3:0] Reserved Local Connect Enable Switch Output Enable
Fh -> SCbus SD_15 Parallel Access Enable (Read/Write) This bit enables the Destination Parallel Access channel to be output in place of the SI Local Bus serial stream. 0 -> Parallel Access Disabled (Default) 1 -> Parallel Access Enabled Switch Output Enable (Read/Write) This bit enables the Switch Output to the SCbus.
[5:4] 6 7
LBDR_[7:0]
[7:0]
Definition
Serial Data Bit [1:8]
Port Select [3:0] (Read/Write) This field selects the SCbus Port that is routed to a Source Channel. 0h -> SCbus SD_0 (Default) 1h -> SCbus SD_1
Serial Data [1:8] (Read Only) This register contains the byte received from the Source Channel selected by the Source Routing Memory. Note: When converted from serial to parallel, bit 1 is received first.
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Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
CONFIGURATION REGISTERS Configuration Register Byte 0, IAR = 00H
LBDR_[7:0] 0 1 2 3 [5:4] [7:6] C_[7:0] 0 1 2 3 [5:4] [7:6] Definition SCbus Clock Master SCbus Clock Master Arm SCbus Primary/ Alternate Select Diagnostic Mode Enable SCbus Framing Mode [1:0] Local Bus Framing Mode [1:0]
SC4000
Configuration Register Byte 1, IAR = 01H
LBDR_[7:0] [2:0] 3 C_[15:8] [10:8] 11 Definition Master Clock Input Frequency Select [2:0] Direct R/W to Parallel Access Registers Enable Message Channel Registered TXD Enable Message Channel TXD_0 or TXD_1 (internal HDLC) Select Message Channel Clock Duty Cycle Select Message Channel Output Disable (w/Loopback)
SCbus Primary/Alternate Select (C_2) (Read/Write) The SC4000 provides Alternate SCbus signals for fault tolerance. This bit controls internal signal selection. 0->Primary SCbus signals selected (Default) 1->Alternate SCbus Signals selected Diagnostic Mode Enable (C_3) (Read/Write) In Diagnostic Mode the SC4000's SCbus output drivers and receivers are electrically disconnected from the SCbus. Internally, the SCbus outputs are looped back to their corresponding inputs. This creates a virtual SCbus within the SC4000 that can be used to test thoroughly the SC4000 without disrupting normal SCbus traffic. 0->Diagnostic Mode Disabled 1->Diagnostic Mode Enabled (default) Note 1: Diagnostic Mode is Enabled when the SC4000 is reset. Note 2: A clock must be present at the Master Clock input to use this mode. SCbus Framing Mode [1:0](C_[5:4]) (Read/Write) 0x -> 2.048 Mb/s, 256 Bits/Frame, 32 Timeslots/Frame (Default) 10 -> 4.096 Mb/s, 512 Bits/Frame, 64 Timeslots/frame 11 -> 8.192 Mb/s, 1024 Bits/Frame, 128 Timeslots/Frame Local bus Framing Mode [1:0](C_[7:6]) (Read/Write) 0x -> 2.048 Mb/s, 256 Bits/Frame, 32 Timeslots/Frame (Default) 10 -> 4.096 Mb/s, 512 Bits/Frame, 64 Timeslots/frame 11 -> 8.192 Mb/s, 1024 Bits/Frame, 128 Timeslots/Frame Note: If the Local Bus framing mode selection is for a higher data rate than that of the SCbus framing mode, then a 65.536 MHz clock must be provided on X_IN.
4 5
12 13
6
14
7
15
SCbus Clock Master (C_0) (Read/Write) This bit is synchronized with the Master Clock Input enables the SC4000 to start and stop being SCbus Clock Master. 0-> SCbus Clock Master Disabled (Default) 1-> SCbus Clock Master Enabled Note: With IAR=00H and LBDR D_0=0 issue Terminate command to asynchronously stop being SCbus Clock Master when no Master Clock Input is present (i.e dead clock) SCbus Clock Master Arm (C_1) (Read/Write) The process of becoming SCbus Clock Master can be sped up by arming the SC4000 which is intended to become clock master in the event of a clock failure. When a SC4000 is armed and CLKFAIL=1 the C_0 bit is automatically set. The SC4000 begins driving the SCbus within 4 clocks of CLKFAIL going high. 0-> SCbus Clock Master Disarmed (Default) 1-> SCbus Clock Master Armed Note: C_51 SCbus CLKFAIL Debounce Enable must be set to use this feature.
Master Clock Input Frequency Select [2:0] (C_[10:8]) (Read/Write) 000-> 2.048 MHz (Default) 001-> 4.096 MHz 010-> 8.192 MHz 011->16.384 MHz 100-> 32.768 MHz 101-> 65.536 MHz 110-> Reserved 111-> Reserved Note: The Master Clock Input may be sourced from either X_IN or CLK_IN (see C_43). Direct R/W to Parallel Access Registers Enable (C_11) (Read/Write) 0-> Direct R/W Disabled (Default) 1-> Direct R/W Enabled Note: When Disabled A_[8:2] is don't care. When Enabled address setup to falling edge of WR_N or STRB_N is required. Message Channel Registered TXD Enable (C_12) (Read/Write) 0-> TXD Passed Through onto MC (Default) 1-> TXD Registered onto MC
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Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
Note: When C_12=0 the HDLC Controller must be programmed to output TXD on the Rising edge of MC_CLK. When C_12=1 the HDLC controller must be programmed to output TXD on the falling edge of MC_CLK. Message Channel TXD_0 or TXD_1 Select (C_13) (Read/Write) 0-> TXD_0 External HDLC Controller (Default) 1-> TXD_1 Future Internal HDLC Controller Note: If TXD_1 is selected on an SC4000 without an Internal HDLC Controller all 1's will be output on MC (idle). Message Channel Clock Duty Cycle Select (C_14) (Read/Write) 0-> 50% (Default) 1-> 75% (2 &4 Mb/s SCbus modes), 62.5% (8 Mb/s SCbus) Note: SCLKX2N must be present to select 75% when SCbus is 2 Mb/s. Message Channel Output Disable (W/ loopback) (C_15) (Read/Write) 0-> Message Channel Output Enabled (Default) 1-> Message Channel Output Disabled Note: When the Message Channel is Disabled, TXD is looped back to the RXD to allow diagnostics runs on the HDLC Controller. Configuration Register Byte 2, IAR = 02H
SC4000
SCbus SD Output Delay Enable (C_18) (Read/Write) To avoid bus contention, enabled SCbus SD outputs are delayed when coming out of tri-state. 0-> SCbus SD Output Delay Disabled (Default) 1-> SCbus SD Output Delay Enabled Local bus SO Output Delay Enable (C_19) (Read/Write) To avoid bus contention, enabled local bus SO outputs are delayed when coming out of tri-state. 0-> Local bus SO Output Delay Disabled (Default) 1-> Local bus SO Output Delay Enabled SCbus FSYNCN Sample Position (C_20) (Read/Write) 0-> Sample at rising edge of SCLK (Default) 1-> Sample at rising edge of SCLKX2N with SCLK high. SCbus FSYNCN Rate (C_21) (Read/Write) This bit determines the clock by which the FSYNCN signal is generated. 0 -> 1 SCLK period (Default) 1 -> 1 SCLKX2N period Note: This mode is provided for MVIP compatibility. SCbus SCLKX2N, SCLKX2NA Output Disable(C_22) (Read/Write) This bit disables the SCLKX2N and SCLKX2NA outputs when they are not required. When disabled, the outputs are tri-stated. 0-> SCLKX2N and SCLKX2NA Outputs Enabled (Default) 1-> SCLKX2N and SCLKX2NA Outputs Disabled
LBDR_[7:0] C_[23:16] Definition
0 1 2 3 4 5 6 16 17 18 19 20 21 22 SCbus SD Sample Position Local bus SI Sample Position SCbus SD Output Delay Enable Local bus SO Output Delay Enable SCbus FSYNCN Sample position SCbus FSYNCN Rate SCbus SCLKX2N, SCLKX2NA Output Disable SCbus Alternate (A) Signals Output Enable
7
23
SCbus SD Sample Position (C_16) (Read/Write) 0-> Sample at 50% of Bit Cell (Default) 1-> Sample at 75% of Bit Cell Note: SCLKX2N must be present to select 75% sample. Local Bus SI Sample Position (C_17) (Read/Write) 0-> Sample at 50% of Bit Cell (Default) 1-> Sample at 75% of Bit Cell Note 1:To select 75% sample,SCLKX2N must be present or the local bus framing mode must be set to a data rate that is either higher or lower than the SCbus framing mode. Note 2:To select 75% sample (C_17=1), it is not necessary to select the L_CLK rate equal to 2X (C_28=1)
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Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SCbus Alternate (A) Signals Output Enable (C_23) (Read/Write) This bit enables the SCbus Alternate ("A") Signals Output (when required). When disabled, the outputs are tri-stated. 0-> SCbus Alternate ("A") Signals Output Disabled (Default) 1-> SCbus Alternate ("A") Signals Output Enabled Configuration Register Byte 3, IAR = 03H
LBDR_[7:0] 0 1 [3:2] 4 5 6 C_[31:24] 24 25 [27:26] 28 29 30 Definition Local bus L_CLK Polarity Local bus L_FS Polarity Local bus L_FS Position [1:0] Local bus L_CLK and L_FS Rate Local bus L_CLK DPLL Enable Local bus L_CLK 8.192 MHz 62.5% duty cycle Enable Reserved (0) (Read only)
SC4000
Configuration Register Byte 4, IAR = 04H
LBDR_[7:0] [3:0] [7:4] C_[39:32] [35:32] [39:36] Definition Revision field (read only) Version field (SC4000 = 1H, SC2000 = 0H) (Read only)
Local bus L_CLK & L_FS Rate (C_28) (Read/Write) 0 -> L_CLK & L_FS equal to the Local bus data rate (Default) 1 -> L_CLK & L_FS equal to 2 times the Local bus data rate Note: To select the 2x rate, SCLKX2N must be present or the Local bus framing mode must be set to a data rate that is either higher or lower than the SCbus framing mode. Local bus L_CLK DPLL Enable (C_29) (Read/Write) This mode is provided to maintain a continuous L_CLK for network interfaces during a Clock Fail condition. 0->L_CLK DPLL Disabled (Default) 1->L_CLK DPLL Enabled Note 1: The Local bus Framing Mode (C_[7:6]) must be set to 2.048 Mb/s and a 65.536MHz Clock must be supplied on X_IN. Note 2: When Enabled L_CLK will run free during an SCbus Clock Fail condition. Note 3: When the DPLL enters the freerun, the Local bus SO lines are tri-stated. Local bus L_CLK 8.192 MHz 62.5% Duty Cycle (C_30) (Read/Write) 0 -> L_CLK 8.192 MHz 62.5% Duty Cycle Disabled (Default) 1 -> L_CLK 8.192 MHz 62.5% Duty Cycle Enabled Note: To enable L_CLK 8.192 MHz 62.5% Duty Cycle, the Local bus Framing Mode (C_[7:6]) must be set to 8.192 Mb/s and the SCbus Framing Mode (C_[5:4]) must be set to 4.096 Mb/s or 2.048 Mb/s. C_28 must be set to 0.
Version/Revision Status (C_[39:32]) The Version/Revision Register is a read only register. It is intended for use to identify SCxxxx devices. This field may be changed in future SCxxxx designs. It is recommended that a test of this field be included in all versions of firmware interface code. The initial release of the SC4000 will be Version/Revision = 10H Configuration Register 5,IAR = 05H
LBDR_[7:0] [2:0] 3 [5:4] 6 7 C_[47:40] [42:40] 43 [45:44] 46 47 Definition Master PLL Reference Select [2:0] Internal/External Master PLL Select SCbus SREF_8K Source Select [1:0] SCbus SREF_8K Output Enable SCbus SCLK 8.192 MHz 62.5% duty cycle enable
7
31
Local bus L_CLK Polarity (C_24) (Read/Write) 0- > L_CLK Non-Inverted (Default) 1- > L_CLK Inverted Local bus L_FS Polarity (C_25) (Read/Write) 0- > L_FS Non-Inverted (Default) 1- > L_FS Inverted Local bus L_FS Position (C_[27:26]) (Read/Write) 00 -> L_FS occurs during the last clock period of the frame (Default) 01 -> L_FS straddles the frame boundary 10 -> L_FS occurs during the first clock period of the frame 11 -> Reserved
Master PLL Reference Select [2:0] (C_[42:40]) (Read/Write) When C_43=0 this field selects the reference for the Internal Master PLL. 000 -> Free-run (Default) 001 -> Free-run 010 -> Free-run 011 -> SREF_8K 100 -> REF_8K_0 101 -> REF_8K_1 110 -> REF_8K_2 111 -> REF_8K_3
2000 Sep 07
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Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
When C_43=1 this field selects the reference for the External Master PLL which is output on REF_8K_OUT pin7. 000 ->Free-run (driven high) (Default) 001 ->Free-run (driven high) 010 ->Free-run (driven high) 011 -> SREF_8K 100 -> REF_8K_0 101 -> REF_8K_1 110 -> tri-state (Z) 111 -> tri-state (Z) Internal/External Master PLL Select (C_43) (Read/Write) This bit selects the Master PLL to be either Internal or External. 0 -> Internal Master PLL (Default) 1 -> External Master PLL SCbus SREF_8K Source Select [1:0] (C_[45:44]) (Read/Write) 00 -> REF_8K_0 (Default) 01 -> REF_8K_1 10 -> REF_8K_2 11 -> REF_8K_3 SCbus SREF_8K Output Enable (C_46) (Read/Write) 0 -> SCbus SREF_8K Disabled (Z) (Default) 1 -> SCbus SREF_8K Enabled SCbus SCLK 8.192 MHz 62.5% Duty Cycle (C_47) (Read/Write) 0 -> SCLK 8.192 MHz 62.5% Duty Cycle Disabled (Default) 1 -> SCLK 8.192 MHz 62.5% Duty Cycle Enabled Note: The SCbus Framing Mode (C_[5:4]) must be set to 8.192 Mb/s to enable SCLK 8.192 MHz 62.5% duty cycle. If Enable (C_22=0) SCLKX2N will be driven high. Clock Watchdog Enable (C_48) (Read/Write) This bit enables the Clock Watchdog. 0 -> Clock Watchdog Disabled (Default) 1 -> Clock Watchdog Enabled Note: When enabled, C_48 is read back a 1 until the Master PLL clocks for 125us (+/- 50%); then it reads back a 0. This mode is provided to allow detection of a missing PLL clock. This information can then be used to take a master off the bus or to remove a secondary clock master from the fallback list. The Clock Watchdog must be re-armed after each test. To re-arm, the Clock Watchdog C_48 must be cleared to "0" and then set to "1". Microprocessor Watchdog Enable (C_49) (Read/Write) This bit enables the Microprocessor Watchdog. 0 -> Microprocessor Watchdog Disabled (Default) 1 -> Microprocessor Watchdog Enabled Note: When enabled the SC4000 will be put into reset after the Master PLL clocks for 256 ms (+/-50%).
4 5 6 7 52 53 54 55 3 51 2 50
SC4000
This mode is provided to force an SC4000 off the SCbus when it's controlling microprocessor fail to reset the watchdog. Each time C_49 is cleared "0" and the set "1" the watchdog count is reset. SCbus CLKFAIL Latch Set Polarity Select (C_50) (Read/Write) This bit selects the polarity of the SCbus CLKFAIL signal that will set the CLKFAIL latch. 0 -> CLKFAIL latch set when CLKFAIL = 0 (Default) 1 -> CLKFAIL latch set when CLKFAIL = 1 Note 1: The CLKFAIL polarity bit can be used to generate interrupts on both ends of a CLKFAIL transition. The CLKFAIL = 0 interrupt is used by the new primary clock source to determine that the transition from secondary to primary has been made. The CLKFAIL = 1 interrupt is used by a secondary clock source to determine that the primary clock source has given up the bus. A third module (neither primary or secondary) could use this interrupt to monitor the CLKFAIL transition and act as a system watchdog. Note 2: Only change CLKFAIL polarity when CLKFAIL Latch Clear_N (C_60) = 0. SCbus CLKFAIL Latch Debounce Enable (C_51) (Read/Write) 0 -> CLKFAIL Latch Debounce Disabled (Default) 1 -> CLKFAIL Latch Debounce Enabled Note 1: A clock must be present from the Master PLL to enable this feature. Note 2: The debounce logic requires that the CLKFAIL signal be sampled with the same value for two consecutive Master PLL clocks before it can set the CLKFAIL Latch.
Configuration Register Byte 6, IAR = 06H
LBDR_[7:0] 0 1 C_[55:48] 48 49 Definition Clock Watchdog Enable Microprocessor Watchdog Enable SCbus CLKFAIL Latch Set Polarity Select SCbus CLKFAIL Latch Debounce Enable Frame Boundary Latch Set Delay Enable INT_0 Mask_n INT_0 Polarity INT_0 Output Driver Configuration
2000 Sep 07
30
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
Frame Boundary Latch Set Delay Enable (C_52) (Read/Write) 0 -> Frame Boundary Latch Set at frame boundary - no delay (Default) 1 -> Frame Boundary Latch Set is delayed until after the input buffer to output buffer transfer is complete (4 internal clocks after frame boundary). Note 1: With direct W/R to Parallel Access Register Enabled (C_11=1), using the delayed frame boundary interrupt indicates that it is now safe to read from and write to the Parallel Access Registers. To avoid data corruption, all access must be completed 8 internal clocks prior to the next delayed frame boundary interrupt. Note 2: The internal clock is equal to either the SCbus data rate or the Local bus data rate whichever is faster. INT_0 Mask_N (C_53) (Read/Write) Clearing this bit("0") masks INT_0. INT_0 is the logical OR of CLKFAIL (C_56), Frame Boundary (C_57), Internal Master PLL Error (C_58) Latches and SCbus Error (C_59) Indicator. 0 -> INT_0 Masked (Default) 1 -> INT_0 Enabled Note: The INT_0 Mask bit can be used to globally disable interrupt generation while the state of the latches can continue to be polled through the microprocessor interface. This bit can also be used to create edge-triggered interrupts. INT_0 Output Polarity (C_54) (Read/Write) 0 -> INT_0 Active Low (Default) 1 -> INT_0 Active High INT_0 Output Driver (C_55) (Read/Write) 0 -> Open Collector INT_0 Output Driver (Default) 1 -> Totem-Pole INT_0 Output Driver Configuration Register Byte 7, IAR = 07H
LBDR_[7:0] 0 1 2 C_[63:56] 56 57 58 Definition SCbus CLKFAIL Latch (Read only) Frame Boundary Latch (Read only) Internal Master PLL Error Latch (Read only) SCbus Error Indicator (Read only) SCbus CLKFAIL Latch Clear_n Frame Boundary Latch Clear_n Internal Master PLL Error Latch Clear_n Reserved (0) (Read only)
SC4000
SCbus CLKFAIL Latch Clear_N (C_60) (Read/Write) 0 -> SCbus CLKFAIL Latch held clear (Default) 1 -> SCbus CLKFAIL Latch enabled Frame Boundary Latch Clear_N (C_61) (Read/Write) 0 -> Frame Boundary Latch held clear (Default) 1 -> Frame Boundary Latch enabled Internal Master PLL Error Latch Clear_N (C_62) (Read/Write) 0 -> Internal Master PLL Error Latch held clear (Default) 1 -> Internal Master PLL Error Latch enabled Configuration Register Byte 8, IAR = 08H
LBDR_[7:0] C_[71:64] 64 Definition SCbus SCLKX2N Error Latch (Read only) SCbus SCLKX2NA Error Latch (Read only) SCbus SCLK Error Latch (Read only) SCbus SCLKA Error Latch (Read only) SCbus SCLKX2N Error Latch Clear_n SCbus SCLKX2NA Error Latch Clear_n SCbus SCLK Error Latch Clear_n SCbus SCLKA Error Latch Clear_n
3 4 5 6 7
59 60 61 62 63
SCbus CLKFAIL Latch (C_56) (Read Only) 0 -> SCbus CLKFAIL Latch Clear 1 -> SCbus CLKFAIL Latch Set
0
1
65
Frame Boundary Latch (C_57) (Read only) 0 -> Frame Boundary Latch Clear 1 -> Frame Boundary Latch Set Internal Master PLL Error Latch (C_58) (Read Only) This latch is set when the Internal Master PLL is not "locked" to its selected reference. 0 -> Internal Master PLL Error Latch Clear 1 -> Internal Master PLL Error Latch Set SCbus Error Indicator (C_59) (Read Only) C_59 is the logical OR of C_[67:64], C_[74:72] and C_[83:80]. 0 -> All SCbus Error Latches Clear 1 -> one or more SCbus Error Latches Set
7 71 2 3 4 5 6 66 67 68 69 70
SCbus SCLKX2N Error Latch (C_64) (Read Only) The SCbus SCLKX2N Error Latch is set when SCLKX2N does not transition during the equivalent Master PLL clock period. 0 -> SCbus SCLKX2N Error Latch Clear 1 -> SCbus SCLKX2N Error Latch Set
2000 Sep 07
31
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SCbus SCLKX2NA Error Latch (C_65) (Read only) The SCbus SCLKX2NA Error Latch is set when SCLKX2NA does not transition during the equivalent Master PLL clock period. 0 -> SCbus SCLKX2NA Error Latch Clear 1 -> SCbus SCLKX2NA Error Latch Set SCbus SCLK Error Latch (C_66) (Read only) The SCbus SCLK Error Latch is set when SCLK does not transition during the equivalent Master PLL clock period. 0 -> SCbus SCLK Error Latch Clear 1 -> SCbus SCLK Error Latch Set SCbus SCLKA Error Latch (C_67) (Read only) The SCbus SCLKA Error Latch is set when SCLKA does not transition during the equivalent Master PLL clock period. 0 -> SCbus SCLKA Error Latch Clear 1 -> SCbus SCLKA Error Latch Set SCbus SCLKX2N Error Latch Clear_N (C_68) (Read/Write) 0 ->SCbus SCLKX2N Error Latch held clear (Default) 1 ->SCbus SCLKX2N Error Latch enabled SCbus SCLKX2NA Error Latch Clear_N (C_69) (Read/Write) 0 ->SCbus SCLKX2NA Error Latch held clear (Default) 1 ->SCbus SCLKX2NA Error Latch enabled SCbus SCLK Error Latch Clear_N (C_70) (Read/Write) 0 ->SCbus SCLK Error Latch held clear (Default) 1 ->SCbus SCLK Error Latch enabled SCbus SCLKA Error Latch Clear_N(C_71) (Read/Write) 0 ->SCbus SCLKA Error Latch held clear (Default) 1 ->SCbus SCLKA Error Latch enabled SCbus FSYNCN Error Latch (C_72) (Read Only) The SCbus FSYNCN Error Latch is set when FSYNCN does not transition during the equivalent Master PLL clock period. 0 ->SCbus FSYNCN Error Latch Clear 1 ->SCbus FSYNCN Error Latch Set SCbus FSYNCNA Error Latch (C_73) (Read Only) The SCbus FSYNCNA Error Latch is set when FSYNCNA does not transition during the equivalent Master PLL clock period. 0 ->SCbus FSYNCNA Error Latch Clear 1 ->SCbus FSYNCNA Error Latch Set SCbus Clock Master Error Latch (C_74) (Read Only) The SCbus Clock Master Error Latch is set when the SC4000 is configured to be Clock Master and the internally generated frame sync signal and SCbus FSYNCN are not equal. This feature is provided to detect when more than one SCbus device is enabled as Clock Master
5 85 1 81
SC4000
(i.e. two device driving FSYNCN). 0 ->SCbus Clock Master Error Latch Clear 1 ->SCbus Clock Master Error Latch Set SCbus FSYNCN Error Latch Clear_N (C_76) (Read/Write) 0 ->SCbus FSYNCN Error Latch held clear (Default) 1 ->SCbus FSYNCN Error Latch enabled SCbus FSYNCNA Error Latch Clear_N (C_77) (Read/Write) 0 ->SCbus FSYNCNA Error Latch held clear 1 ->SCbus FSYNCNA Error Latch enabled SCbus Clock Master Error Latch Clear_N (C_78) (Read/Write) 0 ->SCbus Clock Master Error Latch held clear (Default) 1 ->SCbus Clock Master Error Latch enabled Configuration Register Byte 10, IAR = 0AH
LBDR_[7:0] 0 C_[87:80] 80 Definition SCbus SREF_8K NE SREF_8KA Error Latch (Read only) SCbus CLKFAIL NE CLKFAILA Error Latch (Read only) SCbus MC NE MCA Error Latch (Read only) SCbus SD Error Indicator (Read only) SCbus SREF_8K NE SREF_8KA Error Latch Clear_n SCbus CLKFAIL NE CLKFAILA Error Latch Clear_n SCbus MC NE MCA Error Latch Clear_n SCbus SD Error Latch Clear_n
Configuration Register Byte 9, IAR = 09H
LBDR_[7:0] 0 C_[79:72] 72 Definition SCbus FSYNCN Error Latch (Read Only) SCbus FSYNCNA Error Latch (Read Only) SCbus Clock Master Error Latch (Read Only) Reserved (0) (Read Only) SCbus FSYNCN Error Latch Clear_n SCbus FSYNCNA Error Latch Clear_n SCbus Clock Master Error Latch Clear_n Reserved (0) (Read Only)
1
73
2
74
3 4 5 6
75 76 77 78
7
79
2
82
3 4
83 84
6 7
86 87
NE: Not Equal
2000 Sep 07
32
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SCbus SREF_8K NE SREF_8KA Error Latch (C_80)(Read only) The SCbus SREF_8K NE SREF_8KA Error Latch is set when SREF_8K and SREF_8KA are not equal for three consecutive Master PLL clocks. 0 ->SCbus SREF_8K NE SREF_8KA Error Latch Clear 1 ->SCbus SREF_8K NE SREF_8KA Error Latch Set SCbus CLKFAIL NE CLKFAILA Error Latch (C_81)(Read only) The SCbus CLKFAIL NE CLKFAILA Error Latch is set when CLKFAIL and CLKFAILA are not equal for three consecutive Master PLL clocks. 0 ->SCbus CLKFAIL NE CLKFAILA Error Latch Clear 1 ->SCbus CLKFAIL NE CLKFAILA Error Latch Set SCbus MC NE MCA Error Latch (C_82) (Read only) The SCbus MC NE MCA Error Latch is set when MC and MCA are not equal. MC_CLK is used to sample the comparison. 0 ->SCbus MC NE MCA Error Latch Clear 1 ->SCbus MC NE MCA Error Latch Set SCbus SD Error Indicator (C_83) (Read only) C_83 is the logical OR of C_[103:88] 0 -> All SCbus SD Error Latches Clear 1 -> One or more SCbus SD Error Latch Set SCbus SREF_8K NE SREF_8KA Error Latch Clear_N (C_84)(Read/Write) 0 ->SCbus SREF_8K NE SREF_8KA Error Latch held clear (Default) 1 ->SCbus SREF_8K NE SREF_8KA Error Latch enabled SCbus CLKFAIL NE CLKFAILA Error Latch Clear_N (C_85)(Read/write) 0 ->SCbus CLKFAIL NE CLKFAILA Error Latch held clear (Default) 1 ->SCbus CLKFAIL NE CLKFAILA Error Latch enabled SCbus MC NE MCA Error Latch Clear_N (C_86)(Read/Write) 0 ->SCbus MC NE MCA Error Latch held clear (Default) 1 ->SCbus MC NE MCA Error Latch enabled SCbus SD Error Latch Clear_N (C_87)(Read/Write) 0 ->SCbus SD Error Latch held clear (Default) 1 ->SCbus SD Error Latch enabled Note: C_87 controls all 16 SD Error latches. Configuration Register Byte 11, IAR = 0BH
LBDR_[7:0] [7:0] C_[95:88] [95:88] Definition SCbus SD_[7:0] Error Latch (Read only)
SC4000
SUMMARY OF SC4000 CONFIGURATION REGISTERS Miscellaneous Diagnostic Mode Enable (C_3) (Read/Write) Direct R/W to Parallel Access Registers Enable (C_11) (Read/Write) SC4000 Revision/Version Register (C_[39:32]) (Read only) Master Clock/PLL Master Clock Input Frequency Select [2:0] (C_[10:8]) (Read/Write) Master PLL Reference Select [2:0] (C_[42:40]) (Read/Write) Internal/External Master PLL Select (C_43) (Read/Write) SCbus (MVIP Bus) SCbus Clock Master (C_0) (Read/Write) Scbus Clock Master Arm (C_1) (Read/Write) SCbus Primary/Alternate Select (C_2) (Read/Write SCbus Framing Mode [1:0](C_[5:4]) (Read/Write) SCbus SD Sample Position (C_16) (Read/Write) SCbus SD Output Delay Enable (C_18) (Read/Write) SCbus FSYNCN Sample Position (C_20) (Read/Write) SCbus FSYNCN Rate (C_21) (Read/Write) SCbus SCLKX2N, SCLKX2NA Output Disable (C_22) (Read/Write) SCbus Alternate ("A") Signals Output Enable (C_23) (Read/Write) SCbus SREF_8K Source Select [1:0] (C_[45:44]) (Read/Write SCbus SREF_8K Output Enable (C_46) (Read/Write) SCbus SCLK 8.192 MHz 62.5% Duty Cycle (C_47) (Read/Write)
Configuration Register Byte 12, IAR = 0CH
LBDR_[7:0] [7:0] C_[103:96] [103:96] Definition SCbus SD_[15:8] Error Latch (Read only)
SCbus SD_[15:0] Error Latch (C_[103:88]) (Read only) An SCbus SD Error Latch is set when an SD output timeslot is enabled and the internally generated SD signal and SCbus are not equal. This feature is provided to detect when more than one SCbus device is enabled on the same timeslot. All SCbus SD Error Latches are enabled and cleared by C_87. Note:If multiple destination channels within the same SC4000 are enabled onto the same timeslot anerror will not occur. Bus contention is prevented by logically "ANDing" the internal SD signals before they are output onto the SCbus SD.
2000 Sep 07
33
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
Local Bus Local bus Framing Mode [1:0] (C_[7:6]) (Read/Write) Local Bus SI Sample Position (C_17) (Read/Write) Local bus SO Output Delay Enable (C_19) (Read/Write) Local bus L_CLK Polarity (C_24) (Read/Write) Local bus L_FS Polarity (C_25) (Read/Write) Local bus L_FS Position (C_[27:26]) (Read/Write) Local bus L_CLK & L_FS Rate (C_28) (Read/Write) Local bus L_CLK DPLL Enable (C_29) (Read/Write) Local bus L_CLK 8.192 MHz 62.5% Duty Cycle (C_30) (Read/Write) Message Channel Message Channel Registered TXD Enable (C_12) (Read/Write) Message Channel TXD_0 or TXD_1 Select (C_13) (Read/Write) Message Channel Clock Duty Cycle Select (C_14) (Read/Write) Message Channel Output Disable (W/ loopback) (C_15) (Read/Write) Watchdog Clock Watchdog Enable (C_48) (Read/Write) Microprocessor Watchdog Enable (C_49) (Read/Write) Interrupt SCbus CLKFAIL Latch Set Polarity Select (C_50) (Read/Write) SCbus CLKFAIL Latch Debounce Enable (C_51) (Read/Write) Frame Boundary Latch Set Delay Enable (C_52) (Read/Write) INT_0 Mask_N (C_53) (Read/Write) INT_0 Output Polarity (C_54) (Read/Write) INT_0 Output Driver (C_55) (Read/Write) SCbus CLKFAIL Latch (C_56) (Read Only) Frame Boundary Latch (C_57) (Read only) Internal Master PLL Error Latch (C_58) (Read Only) SCbus Error Indicator (C_59) (Read Only) SCbus CLKFAIL Latch Clear_N (C_60) (Read/Write) Frame Boundary Latch Clear_N (C_61) (Read/Write) Internal Master PLL Error Latch Clear_N (C_62) (Read/Write) SCbus SCLKX2N Error Latch (C_64) (Read Only) SCbus SCLKX2NA Error Latch (C_65) (Read only) SCbus SCLK Error Latch (C_66) (Read only) SCbus SCLKA Error Latch (C_67) (Read only) SCbus SCLKX2N Error Latch Clear_N (C_68) (Read/Write) SCbus SCLKX2NA Error Latch Clear_N (C_69) (Read/Write) SCbus SCLK Error Latch Clear_N (C_70) (Read/Write) SCbus SCLKA Error Latch Clear_N(C_71) (Read/Write SCbus FSYNCN Error Latch (C_72) (Read Only) SCbus FSYNCNA Error Latch (C_73) (Read Only) SCbus Clock Master Error Latch (C_74) (Read Only) SCbus FSYNCN Error Latch Clear_N (C_76) (Read/Write) SCbus FSYNCNA Error Latch Clear_N (C_77) (Read/Write) SCbus Clock Master Error Latch Clear_N (C_78) (Read/Write)
SC4000
SCbus SREF_8K NE SREF_8KA Error Latch (C_80)(Read only) SCbus CLKFAIL NE CLKFAILA Error Latch (C_81)(Read only) SCbus MC NE MCA Error Latch (C_82)(Read only) SCbus SD Error Indicator (C_83) (Read only) SCbus SREF_8K NE SREF_8KA Error Latch Clear_N (C_84)(Read/Write) SCbus CLKFAIL NE CLKFAILA Error Latch Clear_N (C_85)(Read/write) SCbus MC NE MCA Error Latch Clear_N (C_86)(Read/Write) SCbus SD Error Latch Clear_N (C_87)(Read/Write) SCbus SD_[15:0] Error Latch (C_[103:88]) (Read only) Reserved Bit No use Bit (C_31) (Read only) No use Bit (C_63) (Read only) No use Bit (C_75) (Read only) No use Bit (C_79) (Read only) TYPICAL INTERNAL REGISTER ACCESS Typical Write Internal Register Access 1. Read Command/Status register and test for NOT BUSY. (Note1) 2. Write Data into Internal Address register, Low Byte Data register, and High Byte Data register as required. 3. Write a "1" to the WRITE Command bit in the Command/Status register. (Note 4) 4. Read Command/Status register and test for NOT BUSY. (Note 2) Typical Read Internal Register Access 1. Read Command/Status register and test for NOT BUSY. (Note 1) 2. Write Data into Internal Address register. 3. Write a "1" to the READ Command bit in the Command/Status register. (Note 3 & 4)
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Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
4. Read Command/Status register and test for NOT BUSY. (Note2) 5. Read contents of Low Byte Data register and High Byte Data register as required. Note 1:It is not necessary to test for NOT BUSY in this step if the protocol used to access the SC4000 does not allow the previous command to be completed until the Command/Status register indicates NOT BUSY. Note 2:It is not necessary to test for NOT BUSY in this step if the Command given does not require synchronization or if the protocol used to access the SC4000 allows a command to be completed while the Command/Status register indicates BUSY. Note 3:It is not necessary to execute this step if the Command given does not require synchronization. Note 4:The Channel Bank Select field may be changed during the same write cycle which issues a command. The command will effect the register pointed to by the new value in the Channel Bank Select Field. Test The Nand gate test chain is enabled by forcing the TEST pin "high". When in test mode each pin is "nanded" with the preceding pin and output at the end of chain. X_IN REF_8K_0 REF_8K_1 REF_8K_2 REF_8K_3 TXD_0 RXD MC_CLK I_N INT_0 INT_1 CS_0_N CS_1_N RD_N WR_N DACK_N ALE A_0 A_1 A_2 A_3 A_4 D_0 D_1 D_2 D_3 D_4 D_5 D_6 D_7 SCLKX2N SCLKX2NA SCLK SCLKA SREF_8K SREF_8KA FSYNCN FSYNCNA CLKFAIL CLKFAILA SD_0 SD_1 SD_2 SD_3 A_5 A_6 A_7 A_8 DRQ_R SD_4 SD_5 SD_6 SD_7 SD_8 SD_9 SD_10 SD_11 SD_12 SD_13 SD_14 SD_15 MC MCA L_CLK L_FS SO_0 SO_1 SO_2 SO_3 SI_0 SI_1 SI_2 SI_3 RESET DRQ_T
SC4000
2000 Sep 07
35
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings
Symbol Ts Vi PD Parameter Storage Temperature Input Voltage Package Power Dissipation Test Condition Min -65 -0.5 Max 150 7 1 Unit oC V W
SC4000
Recommended Operating Conditions
Symbol TA VDD Parameter Ambient Temperature Supply Voltage Test Condition Min 0 4.75 Max 70 5.25 Unit oC V
DC Electrical Characteristic
Symbol IDD VIH-SCbus VIL-SCbus VHYS-SCbus VIH-TTL VIL-TTL VIH-CMOS VIL-CMOS VOH-SCbus VOL-SCbus VOH-TTL VOL-TTL VOH-CMOS VOL-CMOS IP-SCbus IP-TTL ILI/O CI-TTL CI-CMOS CIO-SCbus CIO-TTL CO-CMOS Parameter Supply Current Input High Voltage - SCbus Input Low Voltage - SCbus Input Hysteresis Voltage-SCbus Input High Voltage -TTL Input Low Voltage -TTL Input High Voltage -CMOS Input Low Voltage -CMOS Output High Voltage -SCbus Output Low Voltage -SCbus Output High Voltage-TTL Output Low Voltage-TTL Output High Voltage-CMOS Output Low Voltage-CMOS Pull-up Current - SCbus Pull-up Current - TTL I/O Leakage Current Input Capacitance-TTL Input Capacitance-CMOS I/O Capacitance-SCbus Output or I/O Capacitance - TT Output Capacitance - CMOS IOH = -24mA IOL = 24mA IOH = -8mA IOL = 8mA IOH = -0.8mA IOL = 0.8mA VPAD = 0V VPAD = 0V VI/O = VDD or VSS -20 -130 VDD - 0.1V VSS + 0.1 V -50 -400 +/- 10 6 7 12 7 6 2.4 0.4 2.6 -0.5 +/- 0.3 2.0 -0.5 0.7 x VDD -0.5 3 0.4 VDD +0.5 0.8 VDD +0.5 0.3 x VDD Test Condition Min Max 100 VDD +0.5 1.65 Unit mA V V V V V V V V V V V V V A A A pF pF pF pF pF
2000 Sep 07
36
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
AC ELECTRICAL CHARACTERISTICS Figure 7. Microprocessor Interface Timing - Intel Bus Mode (Pin I_N = 0), Non-Multiplexed Address t1 CS_0_N RD_N WR_N A_[8:0] t6 D_[7:0] t7 t8 t9 t3 t4
SC4000
t2
t5
Table 7. Microprocessor Interface Timing - Intel Bus Mode
Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 Notes Parameter CS_0_N setup to WR_N WR_N pulse width A_[8:0] setup to WR_N (C_11 = 1) A_[1:0] setup to WR_N (C_11 = 0) A_[8:0] hold from WR_N D_[7:0] setup to WR_N D_[7:0] hold from WR_N D_[7:0] float to valid delay from CS_0_N, RD_N and A_[8:0] D_[7:0] valid to float delay from CS_0_N or RD_N 1. Timing measured with 100 pF load on D_[7:0]. 2. Write cycle may be controlled by CS_0_N or WR_N. 3. ALE = 1. Min 40 40 5 40 5 40 5 0 0 50 20 Typ Max Unit ns ns ns ns ns ns ns ns ns
2000 Sep 07
37
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
Figure 8. Microprocessor Interface Timing - Motorola Bus Mode (Pin I_N = 1), Non-multiplexed Address t1 CS_0_N t2 STRB_N t3 R/W_N t5 t6 A_[8:0] t8 D_[7:0] t9 t10 t11 t7 t4 t3 t4
SC4000
Table 8. Microprocessor Interface Timing - Intel Bus Mode
Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 Notes Parameter CS_0_N setup to STRB_N STRB_N pulse width R/W_N setup to STRB_N R/W_N hold from STRB_N A_[8:0] setup to STRB_N (C_11 = 1) A_[1:0] setup to STRB_N (C_11 = 0) A_[8:0] hold from STRB_N D_[7:0] setup to STRB_N D_[7:0] hold from STRB_N D_[7:0] float to valid delay from CS_0_N, STRB_N and A_[8:0] D_[7:0] valid to float delay from CS_0_N or STRB_N 1. Timing measured with 100 pF load on D_[7:0]. 2. Write cycle may be controlled by CS_0_N or STRB_N. 3. ALE = 1. Min 40 40 5 5 5 40 5 40 5 0 0 50 20 Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns
2000 Sep 07
38
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
Figure 9. Microprocessor Interface Timing - Multiplexed Address
SC4000
t1 ALE t2 A_[8:0] t3
Table 9. Microprocessor Interface Timing - Multiplexed Address
Symbol
t1 t2 t3
Parameter
ALE pulse width A_[8:0] setup to ALE A_[8:0] hold from ALE
Min
20 5 5
Typ
Max
Unit
ns ns ns
2000 Sep 07
39
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
Figure 10. Local Bus Timing, 1XL_CLK Mode (C_28 = 0) Frame Boundary t1 L_CLK t2 L_FS (C_[27:26]=00) L_FS (C_[27:26]=01) L_FS (C_[27:26]=10) SO t6 t7 SI t2 t2 t2 t2 t2 t4 t5
SC4000
t3
Table 10. Local Bus Timing, 1X L_CLK Mode (C_28 = 0)
Symbol t1a t1b t1c t2a t2b t3a t3b t3c t3d t3e t3f t4a t4b t5a t5b t6a t6b t7a t7b Notes Parameter L_CLK Period (C_[7:6] = 0X) L_CLK Period (C_[7:6] = 10) L_CLK Period (C_[7:6] = 11) L_FS delay from L_CLK (C_29 = 0) L_FS delay from L_CLK (C_[7:6] = 0X, C_29 = 1) SO_[3:0] float to valid delay from L_CLK (C_19 = 0, C_29 = 0) SO_[3:0] float to valid delay from L_CLK (C_19 = 0, C_[7:6] = 0X, C_29 = 1) SO_[3:0] float to valid delay from L_CLK (C_19 = 1, C_[7:6] = 0X, C_29 = 0) SO_[3:0] float to valid delay from L_CLK (C_19 = 1, C_[7:6] = 0X, C_29 = 1) SO_[3:0] float to valid delay from L_CLK (C_19 = 1, C_[7:6] = 10) SO_[3:0] float to valid delay from L_CLK (C_19 = 1, C_[7:6] = 11) SO_[3:0] valid to valid delay from L_CLK (C_29 = 0) SO_[3:0] valid to valid delay from L_CLK (C_[7:6] = 0X, C_29 = 1) SO_[3:0] valid to float delay from L_CLK (C_29 = 0) SO_[3:0] valid to float delay from L_CLK (C_[7:6] = 0X, C_29 = 1) SI_[3:0] setup to L_CLK (C_17 = 0, C_29 = 0) SI_[3:0] setup to L_CLK (C_17 = 0, C_[7:6] = 0X, C_29 = 1) SI_[3:0] hold from L_CLK (C_17 = 0, C_29 = 0) SI_[3:0] hold from L_CLK (C_17 = 0, C_[7:6] = 0X, C_29 = 1) 0 -15 0 -15 25 10 25 10 0 -15 0 -15 10 25 10 25 Min Typ 488 244 122 10 25 10 25 60 75 60 30 10 25 10 25 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1. Timing measured with 100 pF load on all Local Bus outputs. 2. L_CLK and L_FS shown with positive polarity, timing is equivalent when signals are inverted.
2000 Sep 07
40
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
Figure 11. Local Bus Timing, 2X L_CLK Mode (C_28=1) Frame Boundary t1 L_CLK t2 L_FS (C_[27:26]=00) L_FS (C_[27:26]=01) L_FS (C_[27:26]=10) SO t6 SI t7 t8 t9 t2 t2 t3 t2 t2 t2 t4 t5
SC4000
Table 11. Local Bus Timing, 2X L_CLK Mode (C_28 = 1)
Symbol t1a t1b t1c t2a t2b t3a t3b t3c t3d t3e t3f t4a t4b t5a t5b t6a t6b t7a t7b t8a t8b t9a t9b Notes Parameter L_CLK Period (C_[7:6] = 0X) L_CLK Period (C_[7:6] = 10) L_CLK Period (C_[7:6] = 11) L_FS delay from L_CLK (C_29 = 0) L_FS delay from L_CLK (C_[7:6] = 0X, C_29 = 1) SO_[3:0] float to valid delay from L_CLK (C_19 = 0, C_29 = 0) SO_[3:0] float to valid delay from L_CLK (C_19 = 0, C_[7:6] = 0X, C_29 = 1) SO_[3:0] float to valid delay from L_CLK (C_19 = 1, C_[7:6] = 0X, C_29 = 0) SO_[3:0] float to valid delay from L_CLK (C_19 = 1, C_[7:6] = 0X, C_29 = 1) SO_[3:0] float to valid delay from L_CLK (C_19 = 1, C_[7:6] = 10) SO_[3:0] float to valid delay from L_CLK (C_19 = 1, C_[7:6] = 11) SO_[3:0] valid to valid delay from L_CLK (C_29 = 0) SO_[3:0] valid to valid delay from L_CLK (C_[7:6] = 0X, C_29 = 1) SO_[3:0] valid to float delay from L_CLK (C_29 = 0) SO_[3:0] valid to float delay from L_CLK (C_[7:6] = 0X, C_29 = 1) SI_[3:0] setup to L_CLK (C_17 = 0, C_29 = 0) SI_[3:0] setup to L_CLK (C_17 = 0, C_[7:6] = 0X, C_29 = 1) SI_[3:0] hold from L_CLK (C_17 = 0,C_29 = 0) SI_[3:0] hold from L_CLK (C_17 = 0, C_[7:6] = 0X, C_29 = 1) SI_[3:0] setup to L_CLK (C_17 = 1, C_29 = 0) SI_[3:0] setup to L_CLK (C_17 = 1, C_[7:6] = 0X, C_29 = 1) SI_[3:0] hold from L_CLK (C_17 = 1, C_29 = 0) SI_[3:0] hold from L_CLK (C_17 = 1, C_[7:6] = 0X, C_29 = 1) 0 -15 0 -15 25 10 25 10 0 -15 0 -15 10 25 10 25 10 25 10 25 Min Typ 244 122 61 10 25 10 25 60 75 60 30 10 25 10 25 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1. Timing measured with 100 pF load on all Local Bus outputs. 2. L_CLK and L_FS shown with positive polarity, timing is equivalent when signals are inverted.
2000 Sep 07
41
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
Figure 12. SCbus Timing t1 SCLKX2N t2 SCLK t5 t3 FSYNCN t7 SD_[15:0] (Output) t10 SD_[15:0] (Input) MC_CLK t15 TXD t17 MC t19 RXD t18 t16 t14 t11 t12 t13 t8 t9 t6 t4 Frame Boundary
SC4000
Table 12. SCbus Timing
Symbol t1a t1b t1c t2a t2b t2c t3 t4 t5 t6 t7a t7b t7c t7d t8 t9 Parameter SCLKX2N Period (C_[5:4] = 0X) SCLKX2N Period (C_[5:4] = 10) SCLKX2N Period (C_[5:4] = 11) SCLK Period (C_[5:4] = 0X) SCLK Period (C_[5:4] = 10) SCLK Period (C_[5:4] = 11) FSYNCN setup to SCLK (C_20 = 0) FSYNCN hold from SCLK (C_20 = 0) FSYNCN setup to SCLKX2N (C_20 = 1) FSYNCN hold from SCLKX2N (C_20 = 1) SD_[15:0] float to valid delay from SCLK (C_18 = 0) SD_[15:0] float to valid delay from SCLK (C_18 = 1, C_[5:4] = 0X) SD_[15:0] float to valid delay from SCLK (C_18 = 1, C_[5:4] = 10) SD_[15:0] float to valid delay from SCLK (C_18 = 1, C_[5:4] = 11) SD_[15:0] valid to valid delay from SCLK SD_[15:0] valid to float delay from SCLK 10 10 10 10 0 25 25 10 0 0 15 60 60 30 15 15 Min Typ 244 122 61 488 244 122 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2000 Sep 07
42
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Symbol t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 Notes
Parameter SD_[15:0] setup to SCLK (C_16 = 0) SD_[15:0] hold from SCLK (C_16 = 0) SD_[15:0] setup to SCLKX2N (C_16 = 1) SD_[15:0] hold from to SCLKX2N (C_16 = 1) MC_CLK delay from SCLK TXD setup to MC_CLK (C_12 = 1) TXD hold from MC_CLK (C_12 = 1) MC delay from MC_CLK (C_12 = 1) MC delay from TXD (C_12 = 0) RXD delay from MC
Min 10 10 10 10 0 10 10 0 0 0
Typ
Max
Unit ns ns ns ns
15
ns ns ns
75 75 15
ns ns ns
1. Timing measured with 100 pF load on all Local Bus outputs, 200 pF load on all SCbus outputs. 2. MC timing measured with 200 pF, 470 pull-up (4.7 k/10). Open collector low to high transitions include 15 ns + 60 ns delay from hi-Z to 3 V. 3. Timing is equivalent when Alternate SCbus signals are selected (C_2=1).
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Figure 13. SCbus Clock Master Timing
SC4000
Frame Boundary SCLKX2N
t1
t1
SCLK t2 FSYNCN t3 t3 t2
Table 13. SCbus Clock Master Timing
Symbol t1 t2 t3 Note Parameter SCLK to SCLKX2N Skew FSYNCN delay from SCLK (C_21 = 0) FSYNCN delay from SCLKX2N (C_21 = 1) 1. Timing measured with 200 pF load on all SCbus outputs. Min -5 0 0 Typ Max 5 10 10 Unit ns ns ns
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Figure 14. SCbus Clock Fail Timing Frame Boundary t3 SCLKX2N t3 SCLK t3 FSYNCN t1 t2 CLKFAIL SD_[15:0] MC Bit 8 Bit 1 Bit 2 t4 t4 t4
SC4000
Table 14. SCbus Clock Fail Timing
Symbol t1 t2a t2b t2c t3 t4 Note Parameter CLKFAIL delay from SCLK CLKFAIL period (C_[5:4] = 0X) CLKFAIL period (C_[5:4] = 10) CLKFAIL period (C_[5:4] = 11) SCLKX2N, SCLK, FSYNCN float delay from CLKFAIL float SCLKX2N, SCLK, FSYNCN valid delay from CLKFAIL 1. Timing measured with 200 pF load on all SCbus outputs. Min -5 488 244 122 15 10 Typ Max 5 Unit
ns ns ns ns ns ns
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Figure 15. REF_8K_[3:0] and SREF_8K input mode Timing t1 REF_8K_[3:0] SREF_8K t2 t3
SC4000
Table 15. REF_8K_[3:0] and SREF_8K Timing
Symbol t1 t2 t3 Note Parameter REF_8K_[3:0] or SREF_8K period REF_8K_[3:0] or SREF_8K high time REF_8K_[3:0] or SREF_8K low time 1. Timing measured with 200 pF load on all SCbus outputs. 100 100 Min Typ 125 Max Unit s ns ns
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SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
SC4000
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Suitability of surface mount IC packages for wave and reflow soldering methods
SC4000
SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable
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DATA SHEET STATUS DATA SHEET STATUS Objective specification PRODUCT STATUS Development DEFINITIONS (1)
SC4000
This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Preliminary specification
Qualification
Product specification
Production
Note 1. Please consult the most recently issued data sheet before initiating or completing a design. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
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NOTES
SC4000
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NOTES
SC4000
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Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000
Internet: http://www.semiconductors.philips.com
SCA 70
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
02/pp52
Date of release: 2000
Sep 07
Document order number:
9397 750 07434

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